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<div class="header">
  <div class="headertitle"><div class="title">RCCEx Exported Macros <div class="ingroups"><a class="el" href="group___s_t_m32_h7xx___h_a_l___driver.html">STM32H7xx_HAL_Driver</a> &raquo; <a class="el" href="group___r_c_c_ex.html">RCCEx</a></div></div></div>
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<div class="contents">
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-groups" class="groupheader"><a id="groups" name="groups"></a>
Topics</h2></td></tr>
<tr class="memitem:RCCEx_5FCRS_5FExtended_5FFeatures" id="r_RCCEx_5FCRS_5FExtended_5FFeatures"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c_ex___c_r_s___extended___features.html">RCCEx CRS Extended Features</a></td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-define-members" class="groupheader"><a id="define-members" name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gacc1a8ad328f57e3dcade01e5355e0add" id="r_gacc1a8ad328f57e3dcade01e5355e0add"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gacc1a8ad328f57e3dcade01e5355e0add">__HAL_RCC_PLL2_ENABLE</a>()</td></tr>
<tr class="memdesc:gacc1a8ad328f57e3dcade01e5355e0add"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macros to enable or disable PLL2.  <br /></td></tr>
<tr class="memitem:ga1e44121d27a8d6096c170d4a2e7c1981" id="r_ga1e44121d27a8d6096c170d4a2e7c1981"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga1e44121d27a8d6096c170d4a2e7c1981">__HAL_RCC_PLL2_DISABLE</a>()</td></tr>
<tr class="memitem:gadee20de14af30b0f958fda51d852066b" id="r_gadee20de14af30b0f958fda51d852066b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gadee20de14af30b0f958fda51d852066b">__HAL_RCC_PLL2CLKOUT_ENABLE</a>(__RCC_PLL2ClockOut__)</td></tr>
<tr class="memdesc:gadee20de14af30b0f958fda51d852066b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)  <br /></td></tr>
<tr class="memitem:ga20869ea15ad0f090d4e3fcc217242474" id="r_ga20869ea15ad0f090d4e3fcc217242474"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga20869ea15ad0f090d4e3fcc217242474">__HAL_RCC_PLL2CLKOUT_DISABLE</a>(__RCC_PLL2ClockOut__)</td></tr>
<tr class="memitem:ga25e0f4d0ef5f525a3c0c5c0a155d0ac6" id="r_ga25e0f4d0ef5f525a3c0c5c0a155d0ac6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga25e0f4d0ef5f525a3c0c5c0a155d0ac6">__HAL_RCC_PLL2FRACN_ENABLE</a>()</td></tr>
<tr class="memdesc:ga25e0f4d0ef5f525a3c0c5c0a155d0ac6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.  <br /></td></tr>
<tr class="memitem:ga320b2becbdbe9830622f1b96526a5d7b" id="r_ga320b2becbdbe9830622f1b96526a5d7b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga320b2becbdbe9830622f1b96526a5d7b">__HAL_RCC_PLL2FRACN_DISABLE</a>()</td></tr>
<tr class="memitem:ga1b17f7d45a505cc6acce76a1a80d9aca" id="r_ga1b17f7d45a505cc6acce76a1a80d9aca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga1b17f7d45a505cc6acce76a1a80d9aca">__HAL_RCC_PLL2_CONFIG</a>(__PLL2M__,  __PLL2N__,  __PLL2P__,  __PLL2Q__,  __PLL2R__)</td></tr>
<tr class="memdesc:ga1b17f7d45a505cc6acce76a1a80d9aca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to configures the PLL2 multiplication and division factors.  <br /></td></tr>
<tr class="memitem:gac2cb75d60618ffea824634490f9d81eb" id="r_gac2cb75d60618ffea824634490f9d81eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gac2cb75d60618ffea824634490f9d81eb">__HAL_RCC_PLL2FRACN_CONFIG</a>(__RCC_PLL2FRACN__)</td></tr>
<tr class="memdesc:gac2cb75d60618ffea824634490f9d81eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.  <br /></td></tr>
<tr class="memitem:ga88d12a5c64e4a820268b9f7f50d74179" id="r_ga88d12a5c64e4a820268b9f7f50d74179"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga88d12a5c64e4a820268b9f7f50d74179">__HAL_RCC_PLL2_VCIRANGE</a>(__RCC_PLL2VCIRange__)</td></tr>
<tr class="memdesc:ga88d12a5c64e4a820268b9f7f50d74179"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to select the PLL2 reference frequency range.  <br /></td></tr>
<tr class="memitem:ga5b448c0dab856525467ba9146db00432" id="r_ga5b448c0dab856525467ba9146db00432"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga5b448c0dab856525467ba9146db00432">__HAL_RCC_PLL2_VCORANGE</a>(__RCC_PLL2VCORange__)</td></tr>
<tr class="memdesc:ga5b448c0dab856525467ba9146db00432"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to select the PLL2 reference frequency range.  <br /></td></tr>
<tr class="memitem:gac7c3a26323f470a939b021ad76f29518" id="r_gac7c3a26323f470a939b021ad76f29518"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gac7c3a26323f470a939b021ad76f29518">__HAL_RCC_PLL3_ENABLE</a>()</td></tr>
<tr class="memdesc:gac7c3a26323f470a939b021ad76f29518"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macros to enable or disable the main PLL3.  <br /></td></tr>
<tr class="memitem:ga9eccd5f7fbfd12da15ba7d76d9a21d18" id="r_ga9eccd5f7fbfd12da15ba7d76d9a21d18"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga9eccd5f7fbfd12da15ba7d76d9a21d18">__HAL_RCC_PLL3_DISABLE</a>()</td></tr>
<tr class="memitem:ga35af940f02bf692f69ca9cf2dd598f24" id="r_ga35af940f02bf692f69ca9cf2dd598f24"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga35af940f02bf692f69ca9cf2dd598f24">__HAL_RCC_PLL3FRACN_ENABLE</a>()</td></tr>
<tr class="memdesc:ga35af940f02bf692f69ca9cf2dd598f24"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.  <br /></td></tr>
<tr class="memitem:ga4a2fb65aefcf9fd35d55a5de8000173e" id="r_ga4a2fb65aefcf9fd35d55a5de8000173e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga4a2fb65aefcf9fd35d55a5de8000173e">__HAL_RCC_PLL3FRACN_DISABLE</a>()</td></tr>
<tr class="memitem:ga44dba3c4e64245e760eb3e780096b4da" id="r_ga44dba3c4e64245e760eb3e780096b4da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga44dba3c4e64245e760eb3e780096b4da">__HAL_RCC_PLL3CLKOUT_ENABLE</a>(__RCC_PLL3ClockOut__)</td></tr>
<tr class="memdesc:ga44dba3c4e64245e760eb3e780096b4da"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)  <br /></td></tr>
<tr class="memitem:ga36d6e5c5786cab7644e5149d00f704c3" id="r_ga36d6e5c5786cab7644e5149d00f704c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga36d6e5c5786cab7644e5149d00f704c3">__HAL_RCC_PLL3CLKOUT_DISABLE</a>(__RCC_PLL3ClockOut__)</td></tr>
<tr class="memitem:gac5020a08025c53436a32d77640786d5d" id="r_gac5020a08025c53436a32d77640786d5d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gac5020a08025c53436a32d77640786d5d">__HAL_RCC_PLL3_CONFIG</a>(__PLL3M__,  __PLL3N__,  __PLL3P__,  __PLL3Q__,  __PLL3R__)</td></tr>
<tr class="memdesc:gac5020a08025c53436a32d77640786d5d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to configures the PLL3 multiplication and division factors.  <br /></td></tr>
<tr class="memitem:ga3c6bb3051b93d8f3051ace7b1611c5c1" id="r_ga3c6bb3051b93d8f3051ace7b1611c5c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga3c6bb3051b93d8f3051ace7b1611c5c1">__HAL_RCC_PLL3FRACN_CONFIG</a>(__RCC_PLL3FRACN__)</td></tr>
<tr class="memdesc:ga3c6bb3051b93d8f3051ace7b1611c5c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.  <br /></td></tr>
<tr class="memitem:ga5825c7707fdbf1432a215fbf3ef4b766" id="r_ga5825c7707fdbf1432a215fbf3ef4b766"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga5825c7707fdbf1432a215fbf3ef4b766">__HAL_RCC_PLL3_VCIRANGE</a>(__RCC_PLL3VCIRange__)</td></tr>
<tr class="memdesc:ga5825c7707fdbf1432a215fbf3ef4b766"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to select the PLL3 reference frequency range.  <br /></td></tr>
<tr class="memitem:ga7c53c8f29406ecd9c45434db4b2af32d" id="r_ga7c53c8f29406ecd9c45434db4b2af32d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga7c53c8f29406ecd9c45434db4b2af32d">__HAL_RCC_PLL3_VCORANGE</a>(__RCC_PLL3VCORange__)</td></tr>
<tr class="memdesc:ga7c53c8f29406ecd9c45434db4b2af32d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to select the PLL3 reference frequency range.  <br /></td></tr>
<tr class="memitem:ga0c98df7eb7d710df2bf05427a4a10bc7" id="r_ga0c98df7eb7d710df2bf05427a4a10bc7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga0c98df7eb7d710df2bf05427a4a10bc7">__HAL_RCC_SAI1_CONFIG</a>(__RCC_SAI1CLKSource__)</td></tr>
<tr class="memdesc:ga0c98df7eb7d710df2bf05427a4a10bc7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to Configure the SAI1 clock source.  <br /></td></tr>
<tr class="memitem:ga9af45dae7c2f2f1c8848be68d7bded7e" id="r_ga9af45dae7c2f2f1c8848be68d7bded7e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga9af45dae7c2f2f1c8848be68d7bded7e">__HAL_RCC_GET_SAI1_SOURCE</a>()</td></tr>
<tr class="memdesc:ga9af45dae7c2f2f1c8848be68d7bded7e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the SAI1 clock source.  <br /></td></tr>
<tr class="memitem:ga6cf17efbf8f472437732901308320283" id="r_ga6cf17efbf8f472437732901308320283"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga6cf17efbf8f472437732901308320283">__HAL_RCC_SPDIFRX_CONFIG</a>(__RCC_SPDIFCLKSource__)</td></tr>
<tr class="memdesc:ga6cf17efbf8f472437732901308320283"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to Configure the SPDIFRX clock source.  <br /></td></tr>
<tr class="memitem:gad3ddc626288e3b401da0b8547f2ac0d3" id="r_gad3ddc626288e3b401da0b8547f2ac0d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gad3ddc626288e3b401da0b8547f2ac0d3">__HAL_RCC_GET_SPDIFRX_SOURCE</a>()</td></tr>
<tr class="memdesc:gad3ddc626288e3b401da0b8547f2ac0d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the SPDIFRX clock source.  <br /></td></tr>
<tr class="memitem:gafd775b802b35eddc3763819b696c8dc6" id="r_gafd775b802b35eddc3763819b696c8dc6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gafd775b802b35eddc3763819b696c8dc6">__HAL_RCC_I2C1235_CONFIG</a>(__I2C1235CLKSource__)</td></tr>
<tr class="memdesc:gafd775b802b35eddc3763819b696c8dc6"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the I2C1/2/3/5* clock (I2C123CLK).  <br /></td></tr>
<tr class="memitem:ga1c11406787c87ef39597619fae00bd88" id="r_ga1c11406787c87ef39597619fae00bd88"><td class="memItemLeft" align="right" valign="top"><a id="ga1c11406787c87ef39597619fae00bd88" name="ga1c11406787c87ef39597619fae00bd88"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>__HAL_RCC_I2C123_CONFIG</b>&#160;&#160;&#160;<a class="el" href="#gafd775b802b35eddc3763819b696c8dc6">__HAL_RCC_I2C1235_CONFIG</a></td></tr>
<tr class="memitem:ga18d44d4471dc6940cdfa9ee4ad4025d3" id="r_ga18d44d4471dc6940cdfa9ee4ad4025d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga18d44d4471dc6940cdfa9ee4ad4025d3">__HAL_RCC_GET_I2C1235_SOURCE</a>()</td></tr>
<tr class="memdesc:ga18d44d4471dc6940cdfa9ee4ad4025d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the I2C1/2/3/5* clock source.  <br /></td></tr>
<tr class="memitem:ga702d7cc3defaf9a4e69ab5ec4a262436" id="r_ga702d7cc3defaf9a4e69ab5ec4a262436"><td class="memItemLeft" align="right" valign="top"><a id="ga702d7cc3defaf9a4e69ab5ec4a262436" name="ga702d7cc3defaf9a4e69ab5ec4a262436"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>__HAL_RCC_GET_I2C123_SOURCE</b>&#160;&#160;&#160;<a class="el" href="#ga18d44d4471dc6940cdfa9ee4ad4025d3">__HAL_RCC_GET_I2C1235_SOURCE</a></td></tr>
<tr class="memitem:ga7cd89ab045ec9b7d5bda7da3e1587828" id="r_ga7cd89ab045ec9b7d5bda7da3e1587828"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga7cd89ab045ec9b7d5bda7da3e1587828">__HAL_RCC_I2C1_CONFIG</a>&#160;&#160;&#160;__HAL_RCC_I2C123_CONFIG</td></tr>
<tr class="memdesc:ga7cd89ab045ec9b7d5bda7da3e1587828"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the I2C1 clock (I2C1CLK).  <br /></td></tr>
<tr class="memitem:gabc9e99366b5dfab7a6c535f8f48af8d3" id="r_gabc9e99366b5dfab7a6c535f8f48af8d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gabc9e99366b5dfab7a6c535f8f48af8d3">__HAL_RCC_GET_I2C1_SOURCE</a>&#160;&#160;&#160;__HAL_RCC_GET_I2C123_SOURCE</td></tr>
<tr class="memdesc:gabc9e99366b5dfab7a6c535f8f48af8d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the I2C1 clock source.  <br /></td></tr>
<tr class="memitem:ga96d9bad1e46c94af8387ca6dbfeea357" id="r_ga96d9bad1e46c94af8387ca6dbfeea357"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga96d9bad1e46c94af8387ca6dbfeea357">__HAL_RCC_I2C2_CONFIG</a>&#160;&#160;&#160;__HAL_RCC_I2C123_CONFIG</td></tr>
<tr class="memdesc:ga96d9bad1e46c94af8387ca6dbfeea357"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the I2C2 clock (I2C2CLK).  <br /></td></tr>
<tr class="memitem:gabaa32df2434beb7a446be4aba5c2a06b" id="r_gabaa32df2434beb7a446be4aba5c2a06b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gabaa32df2434beb7a446be4aba5c2a06b">__HAL_RCC_GET_I2C2_SOURCE</a>&#160;&#160;&#160;__HAL_RCC_GET_I2C123_SOURCE</td></tr>
<tr class="memdesc:gabaa32df2434beb7a446be4aba5c2a06b"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the I2C2 clock source.  <br /></td></tr>
<tr class="memitem:ga335a0313bb3a188435b39a11cf7c3eee" id="r_ga335a0313bb3a188435b39a11cf7c3eee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga335a0313bb3a188435b39a11cf7c3eee">__HAL_RCC_I2C3_CONFIG</a>&#160;&#160;&#160;__HAL_RCC_I2C123_CONFIG</td></tr>
<tr class="memdesc:ga335a0313bb3a188435b39a11cf7c3eee"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the I2C3 clock (I2C3CLK).  <br /></td></tr>
<tr class="memitem:ga06f70ebfa24caeb198001d5c02d6dc78" id="r_ga06f70ebfa24caeb198001d5c02d6dc78"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga06f70ebfa24caeb198001d5c02d6dc78">__HAL_RCC_GET_I2C3_SOURCE</a>&#160;&#160;&#160;__HAL_RCC_GET_I2C123_SOURCE</td></tr>
<tr class="memdesc:ga06f70ebfa24caeb198001d5c02d6dc78"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the I2C3 clock source.  <br /></td></tr>
<tr class="memitem:gac63fbd88afa59e3453a7d5d7c32fb1dc" id="r_gac63fbd88afa59e3453a7d5d7c32fb1dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gac63fbd88afa59e3453a7d5d7c32fb1dc">__HAL_RCC_I2C4_CONFIG</a>(__I2C4CLKSource__)</td></tr>
<tr class="memdesc:gac63fbd88afa59e3453a7d5d7c32fb1dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the I2C4 clock (I2C4CLK).  <br /></td></tr>
<tr class="memitem:ga6632a1fbc809f6f6dedde0d36cbaa3c9" id="r_ga6632a1fbc809f6f6dedde0d36cbaa3c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga6632a1fbc809f6f6dedde0d36cbaa3c9">__HAL_RCC_GET_I2C4_SOURCE</a>()</td></tr>
<tr class="memdesc:ga6632a1fbc809f6f6dedde0d36cbaa3c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the I2C4 clock source.  <br /></td></tr>
<tr class="memitem:ga5d331d1d7b05a87debf939ff00d961d5" id="r_ga5d331d1d7b05a87debf939ff00d961d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga5d331d1d7b05a87debf939ff00d961d5">__HAL_RCC_USART16910_CONFIG</a>(__USART16910CLKSource__)</td></tr>
<tr class="memdesc:ga5d331d1d7b05a87debf939ff00d961d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the USART1/6/9* /10* clock (USART16CLK).  <br /></td></tr>
<tr class="memitem:gacc82f34fbb358dd2cad032a06eaf7ede" id="r_gacc82f34fbb358dd2cad032a06eaf7ede"><td class="memItemLeft" align="right" valign="top"><a id="gacc82f34fbb358dd2cad032a06eaf7ede" name="gacc82f34fbb358dd2cad032a06eaf7ede"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>__HAL_RCC_USART16_CONFIG</b>&#160;&#160;&#160;<a class="el" href="#ga5d331d1d7b05a87debf939ff00d961d5">__HAL_RCC_USART16910_CONFIG</a></td></tr>
<tr class="memitem:ga4f9d49aa3d088259c585f7509736818c" id="r_ga4f9d49aa3d088259c585f7509736818c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga4f9d49aa3d088259c585f7509736818c">__HAL_RCC_GET_USART16910_SOURCE</a>()</td></tr>
<tr class="memdesc:ga4f9d49aa3d088259c585f7509736818c"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the USART1/6/9* /10* clock source.  <br /></td></tr>
<tr class="memitem:gad51ff313be41917e24d3b074f56bb0ba" id="r_gad51ff313be41917e24d3b074f56bb0ba"><td class="memItemLeft" align="right" valign="top"><a id="gad51ff313be41917e24d3b074f56bb0ba" name="gad51ff313be41917e24d3b074f56bb0ba"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>__HAL_RCC_GET_USART16_SOURCE</b>&#160;&#160;&#160;<a class="el" href="#ga4f9d49aa3d088259c585f7509736818c">__HAL_RCC_GET_USART16910_SOURCE</a></td></tr>
<tr class="memitem:ga67f80d0a54e4800370619e3247e3ae01" id="r_ga67f80d0a54e4800370619e3247e3ae01"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga67f80d0a54e4800370619e3247e3ae01">__HAL_RCC_USART234578_CONFIG</a>(__USART234578CLKSource__)</td></tr>
<tr class="memdesc:ga67f80d0a54e4800370619e3247e3ae01"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the USART234578 clock (USART234578CLK).  <br /></td></tr>
<tr class="memitem:ga2de2c847f3e490a5b6ac8b1d13b66883" id="r_ga2de2c847f3e490a5b6ac8b1d13b66883"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga2de2c847f3e490a5b6ac8b1d13b66883">__HAL_RCC_GET_USART234578_SOURCE</a>()</td></tr>
<tr class="memdesc:ga2de2c847f3e490a5b6ac8b1d13b66883"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the USART2/3/4/5/7/8 clock source.  <br /></td></tr>
<tr class="memitem:ga5c9ff3bd1509df21975b5a86202efd52" id="r_ga5c9ff3bd1509df21975b5a86202efd52"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga5c9ff3bd1509df21975b5a86202efd52">__HAL_RCC_USART1_CONFIG</a>&#160;&#160;&#160;__HAL_RCC_USART16_CONFIG</td></tr>
<tr class="memdesc:ga5c9ff3bd1509df21975b5a86202efd52"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the USART1 clock (USART1CLK).  <br /></td></tr>
<tr class="memitem:ga241bae96ad4a1ba687b3bf692e04f444" id="r_ga241bae96ad4a1ba687b3bf692e04f444"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga241bae96ad4a1ba687b3bf692e04f444">__HAL_RCC_GET_USART1_SOURCE</a>&#160;&#160;&#160;__HAL_RCC_GET_USART16_SOURCE</td></tr>
<tr class="memdesc:ga241bae96ad4a1ba687b3bf692e04f444"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the USART1 clock source.  <br /></td></tr>
<tr class="memitem:gaba22cefcb74b384a2e2fb3d2c51fae54" id="r_gaba22cefcb74b384a2e2fb3d2c51fae54"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaba22cefcb74b384a2e2fb3d2c51fae54">__HAL_RCC_USART2_CONFIG</a>&#160;&#160;&#160;<a class="el" href="#ga67f80d0a54e4800370619e3247e3ae01">__HAL_RCC_USART234578_CONFIG</a></td></tr>
<tr class="memdesc:gaba22cefcb74b384a2e2fb3d2c51fae54"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the USART2 clock (USART2CLK).  <br /></td></tr>
<tr class="memitem:ga59a86a292df891a219d5d4a8e26a45e9" id="r_ga59a86a292df891a219d5d4a8e26a45e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga59a86a292df891a219d5d4a8e26a45e9">__HAL_RCC_GET_USART2_SOURCE</a>&#160;&#160;&#160;<a class="el" href="#ga2de2c847f3e490a5b6ac8b1d13b66883">__HAL_RCC_GET_USART234578_SOURCE</a></td></tr>
<tr class="memdesc:ga59a86a292df891a219d5d4a8e26a45e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the USART2 clock source.  <br /></td></tr>
<tr class="memitem:gac1a20f806bcd2ec6cc781bab1d99e5b5" id="r_gac1a20f806bcd2ec6cc781bab1d99e5b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gac1a20f806bcd2ec6cc781bab1d99e5b5">__HAL_RCC_USART3_CONFIG</a>&#160;&#160;&#160;<a class="el" href="#ga67f80d0a54e4800370619e3247e3ae01">__HAL_RCC_USART234578_CONFIG</a></td></tr>
<tr class="memdesc:gac1a20f806bcd2ec6cc781bab1d99e5b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the USART3 clock (USART3CLK).  <br /></td></tr>
<tr class="memitem:ga04818c61b18e167ea60f290ab52247db" id="r_ga04818c61b18e167ea60f290ab52247db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga04818c61b18e167ea60f290ab52247db">__HAL_RCC_GET_USART3_SOURCE</a>&#160;&#160;&#160;<a class="el" href="#ga2de2c847f3e490a5b6ac8b1d13b66883">__HAL_RCC_GET_USART234578_SOURCE</a></td></tr>
<tr class="memdesc:ga04818c61b18e167ea60f290ab52247db"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the USART3 clock source.  <br /></td></tr>
<tr class="memitem:ga711b187525b8b788b9f0ca968b1bd648" id="r_ga711b187525b8b788b9f0ca968b1bd648"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga711b187525b8b788b9f0ca968b1bd648">__HAL_RCC_UART4_CONFIG</a>&#160;&#160;&#160;<a class="el" href="#ga67f80d0a54e4800370619e3247e3ae01">__HAL_RCC_USART234578_CONFIG</a></td></tr>
<tr class="memdesc:ga711b187525b8b788b9f0ca968b1bd648"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the UART4 clock (UART4CLK).  <br /></td></tr>
<tr class="memitem:ga9945c36dd4ffce9d8c1b213e56edf80a" id="r_ga9945c36dd4ffce9d8c1b213e56edf80a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga9945c36dd4ffce9d8c1b213e56edf80a">__HAL_RCC_GET_UART4_SOURCE</a>&#160;&#160;&#160;<a class="el" href="#ga2de2c847f3e490a5b6ac8b1d13b66883">__HAL_RCC_GET_USART234578_SOURCE</a></td></tr>
<tr class="memdesc:ga9945c36dd4ffce9d8c1b213e56edf80a"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the UART4 clock source.  <br /></td></tr>
<tr class="memitem:gae6c043e0b4091279d4db065b38b801b1" id="r_gae6c043e0b4091279d4db065b38b801b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gae6c043e0b4091279d4db065b38b801b1">__HAL_RCC_UART5_CONFIG</a>&#160;&#160;&#160;<a class="el" href="#ga67f80d0a54e4800370619e3247e3ae01">__HAL_RCC_USART234578_CONFIG</a></td></tr>
<tr class="memdesc:gae6c043e0b4091279d4db065b38b801b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the UART5 clock (UART5CLK).  <br /></td></tr>
<tr class="memitem:ga2c68fe07259568cba46c14fc4259933d" id="r_ga2c68fe07259568cba46c14fc4259933d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga2c68fe07259568cba46c14fc4259933d">__HAL_RCC_GET_UART5_SOURCE</a>&#160;&#160;&#160;<a class="el" href="#ga2de2c847f3e490a5b6ac8b1d13b66883">__HAL_RCC_GET_USART234578_SOURCE</a></td></tr>
<tr class="memdesc:ga2c68fe07259568cba46c14fc4259933d"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the UART5 clock source.  <br /></td></tr>
<tr class="memitem:ga28d9b1a1ce7ec3639b1d02ca10104704" id="r_ga28d9b1a1ce7ec3639b1d02ca10104704"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga28d9b1a1ce7ec3639b1d02ca10104704">__HAL_RCC_USART6_CONFIG</a>&#160;&#160;&#160;__HAL_RCC_USART16_CONFIG</td></tr>
<tr class="memdesc:ga28d9b1a1ce7ec3639b1d02ca10104704"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the USART6 clock (USART6CLK).  <br /></td></tr>
<tr class="memitem:ga134c539c1f80f684ee9722f08e4c89ea" id="r_ga134c539c1f80f684ee9722f08e4c89ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga134c539c1f80f684ee9722f08e4c89ea">__HAL_RCC_GET_USART6_SOURCE</a>&#160;&#160;&#160;__HAL_RCC_GET_USART16_SOURCE</td></tr>
<tr class="memdesc:ga134c539c1f80f684ee9722f08e4c89ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the USART6 clock source.  <br /></td></tr>
<tr class="memitem:ga60bd7f1550266967e3f87a85afbddb7a" id="r_ga60bd7f1550266967e3f87a85afbddb7a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga60bd7f1550266967e3f87a85afbddb7a">__HAL_RCC_UART7_CONFIG</a>&#160;&#160;&#160;<a class="el" href="#ga67f80d0a54e4800370619e3247e3ae01">__HAL_RCC_USART234578_CONFIG</a></td></tr>
<tr class="memdesc:ga60bd7f1550266967e3f87a85afbddb7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the UART5 clock (UART7CLK).  <br /></td></tr>
<tr class="memitem:ga680abf193deaeff90542affda7d160d4" id="r_ga680abf193deaeff90542affda7d160d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga680abf193deaeff90542affda7d160d4">__HAL_RCC_GET_UART7_SOURCE</a>&#160;&#160;&#160;<a class="el" href="#ga2de2c847f3e490a5b6ac8b1d13b66883">__HAL_RCC_GET_USART234578_SOURCE</a></td></tr>
<tr class="memdesc:ga680abf193deaeff90542affda7d160d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the UART7 clock source.  <br /></td></tr>
<tr class="memitem:ga492a06425e99e15b064d5278cf319722" id="r_ga492a06425e99e15b064d5278cf319722"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga492a06425e99e15b064d5278cf319722">__HAL_RCC_UART8_CONFIG</a>&#160;&#160;&#160;<a class="el" href="#ga67f80d0a54e4800370619e3247e3ae01">__HAL_RCC_USART234578_CONFIG</a></td></tr>
<tr class="memdesc:ga492a06425e99e15b064d5278cf319722"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the UART8 clock (UART8CLK).  <br /></td></tr>
<tr class="memitem:ga56b15263e2d6dcc75b362d96bf2f7397" id="r_ga56b15263e2d6dcc75b362d96bf2f7397"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga56b15263e2d6dcc75b362d96bf2f7397">__HAL_RCC_GET_UART8_SOURCE</a>&#160;&#160;&#160;<a class="el" href="#ga2de2c847f3e490a5b6ac8b1d13b66883">__HAL_RCC_GET_USART234578_SOURCE</a></td></tr>
<tr class="memdesc:ga56b15263e2d6dcc75b362d96bf2f7397"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the UART8 clock source.  <br /></td></tr>
<tr class="memitem:ga2859926bab56d03f5d4bfbf0941a0a3f" id="r_ga2859926bab56d03f5d4bfbf0941a0a3f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga2859926bab56d03f5d4bfbf0941a0a3f">__HAL_RCC_LPUART1_CONFIG</a>(__LPUART1CLKSource__)</td></tr>
<tr class="memdesc:ga2859926bab56d03f5d4bfbf0941a0a3f"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the LPUART1 clock (LPUART1CLK).  <br /></td></tr>
<tr class="memitem:ga193015f4df5fb541bd4fbbc20d1e20ae" id="r_ga193015f4df5fb541bd4fbbc20d1e20ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga193015f4df5fb541bd4fbbc20d1e20ae">__HAL_RCC_GET_LPUART1_SOURCE</a>()</td></tr>
<tr class="memdesc:ga193015f4df5fb541bd4fbbc20d1e20ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the LPUART1 clock source.  <br /></td></tr>
<tr class="memitem:ga3ef78c8916149398bba06596863734ab" id="r_ga3ef78c8916149398bba06596863734ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga3ef78c8916149398bba06596863734ab">__HAL_RCC_LPTIM1_CONFIG</a>(__LPTIM1CLKSource__)</td></tr>
<tr class="memdesc:ga3ef78c8916149398bba06596863734ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the LPTIM1 clock source.  <br /></td></tr>
<tr class="memitem:gad6688c07a2a8c314df547de8caf378bb" id="r_gad6688c07a2a8c314df547de8caf378bb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gad6688c07a2a8c314df547de8caf378bb">__HAL_RCC_GET_LPTIM1_SOURCE</a>()</td></tr>
<tr class="memdesc:gad6688c07a2a8c314df547de8caf378bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the LPTIM1 clock source.  <br /></td></tr>
<tr class="memitem:gabe82d482e8127576b6ce1f331fcc7e1a" id="r_gabe82d482e8127576b6ce1f331fcc7e1a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gabe82d482e8127576b6ce1f331fcc7e1a">__HAL_RCC_LPTIM2_CONFIG</a>(__LPTIM2CLKSource__)</td></tr>
<tr class="memdesc:gabe82d482e8127576b6ce1f331fcc7e1a"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the LPTIM2 clock source.  <br /></td></tr>
<tr class="memitem:ga806f1d6e6a7d741b4d0524aa849f8ed8" id="r_ga806f1d6e6a7d741b4d0524aa849f8ed8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga806f1d6e6a7d741b4d0524aa849f8ed8">__HAL_RCC_GET_LPTIM2_SOURCE</a>()</td></tr>
<tr class="memdesc:ga806f1d6e6a7d741b4d0524aa849f8ed8"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the LPTIM2 clock source.  <br /></td></tr>
<tr class="memitem:gac11efaec3a89a1b6d9696eb6e9e8048e" id="r_gac11efaec3a89a1b6d9696eb6e9e8048e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gac11efaec3a89a1b6d9696eb6e9e8048e">__HAL_RCC_LPTIM345_CONFIG</a>(__LPTIM345CLKSource__)</td></tr>
<tr class="memdesc:gac11efaec3a89a1b6d9696eb6e9e8048e"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the LPTIM3/4/5 clock source.  <br /></td></tr>
<tr class="memitem:ga6b2263ea1e054aee45c85e64dcfeb99f" id="r_ga6b2263ea1e054aee45c85e64dcfeb99f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga6b2263ea1e054aee45c85e64dcfeb99f">__HAL_RCC_GET_LPTIM345_SOURCE</a>()</td></tr>
<tr class="memdesc:ga6b2263ea1e054aee45c85e64dcfeb99f"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the LPTIM3/4/5 clock source.  <br /></td></tr>
<tr class="memitem:ga36174050acd330e879a5d12bdbfb19c4" id="r_ga36174050acd330e879a5d12bdbfb19c4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga36174050acd330e879a5d12bdbfb19c4">__HAL_RCC_LPTIM3_CONFIG</a>&#160;&#160;&#160;<a class="el" href="#gac11efaec3a89a1b6d9696eb6e9e8048e">__HAL_RCC_LPTIM345_CONFIG</a></td></tr>
<tr class="memdesc:ga36174050acd330e879a5d12bdbfb19c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the LPTIM3 clock source.  <br /></td></tr>
<tr class="memitem:ga08d9d85cee6e2656f7a7b0cf920326b8" id="r_ga08d9d85cee6e2656f7a7b0cf920326b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga08d9d85cee6e2656f7a7b0cf920326b8">__HAL_RCC_GET_LPTIM3_SOURCE</a>&#160;&#160;&#160;<a class="el" href="#ga6b2263ea1e054aee45c85e64dcfeb99f">__HAL_RCC_GET_LPTIM345_SOURCE</a></td></tr>
<tr class="memdesc:ga08d9d85cee6e2656f7a7b0cf920326b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the LPTIM3 clock source.  <br /></td></tr>
<tr class="memitem:ga18a22f0e5f811ba9fee8bb2906dfa60b" id="r_ga18a22f0e5f811ba9fee8bb2906dfa60b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga18a22f0e5f811ba9fee8bb2906dfa60b">__HAL_RCC_FMC_CONFIG</a>(__FMCCLKSource__)</td></tr>
<tr class="memdesc:ga18a22f0e5f811ba9fee8bb2906dfa60b"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the FMC clock source.  <br /></td></tr>
<tr class="memitem:ga48733b3d8faeb67777184a503bbbf2fa" id="r_ga48733b3d8faeb67777184a503bbbf2fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga48733b3d8faeb67777184a503bbbf2fa">__HAL_RCC_GET_FMC_SOURCE</a>()</td></tr>
<tr class="memdesc:ga48733b3d8faeb67777184a503bbbf2fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the FMC clock source.  <br /></td></tr>
<tr class="memitem:ga1c690ec86648d92efb97d2598a0cb2f1" id="r_ga1c690ec86648d92efb97d2598a0cb2f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga1c690ec86648d92efb97d2598a0cb2f1">__HAL_RCC_USB_CONFIG</a>(__USBCLKSource__)</td></tr>
<tr class="memdesc:ga1c690ec86648d92efb97d2598a0cb2f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to configure the USB clock (USBCLK).  <br /></td></tr>
<tr class="memitem:ga2b796e523b7f4c4cd7b5f06b7f995315" id="r_ga2b796e523b7f4c4cd7b5f06b7f995315"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga2b796e523b7f4c4cd7b5f06b7f995315">__HAL_RCC_GET_USB_SOURCE</a>()</td></tr>
<tr class="memdesc:ga2b796e523b7f4c4cd7b5f06b7f995315"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the USB clock source.  <br /></td></tr>
<tr class="memitem:ga03642b548896f327c3efc876aff4b349" id="r_ga03642b548896f327c3efc876aff4b349"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga03642b548896f327c3efc876aff4b349">__HAL_RCC_ADC_CONFIG</a>(__ADCCLKSource__)</td></tr>
<tr class="memdesc:ga03642b548896f327c3efc876aff4b349"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to configure the ADC clock.  <br /></td></tr>
<tr class="memitem:ga2ee9f1838a8450f949b548a06ed3bc58" id="r_ga2ee9f1838a8450f949b548a06ed3bc58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga2ee9f1838a8450f949b548a06ed3bc58">__HAL_RCC_GET_ADC_SOURCE</a>()</td></tr>
<tr class="memdesc:ga2ee9f1838a8450f949b548a06ed3bc58"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the ADC clock source.  <br /></td></tr>
<tr class="memitem:gac23e7b662783a7131e3e892ff0c21f06" id="r_gac23e7b662783a7131e3e892ff0c21f06"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gac23e7b662783a7131e3e892ff0c21f06">__HAL_RCC_SWPMI1_CONFIG</a>(__SWPMI1CLKSource__)</td></tr>
<tr class="memdesc:gac23e7b662783a7131e3e892ff0c21f06"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to configure the SWPMI1 clock.  <br /></td></tr>
<tr class="memitem:ga3ddf343654e802758b5e779d81122404" id="r_ga3ddf343654e802758b5e779d81122404"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga3ddf343654e802758b5e779d81122404">__HAL_RCC_GET_SWPMI1_SOURCE</a>()</td></tr>
<tr class="memdesc:ga3ddf343654e802758b5e779d81122404"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the SWPMI1 clock source.  <br /></td></tr>
<tr class="memitem:ga79c4e732154d11fb10e6b5752ab31fc4" id="r_ga79c4e732154d11fb10e6b5752ab31fc4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga79c4e732154d11fb10e6b5752ab31fc4">__HAL_RCC_DFSDM1_CONFIG</a>(__DFSDM1CLKSource__)</td></tr>
<tr class="memdesc:ga79c4e732154d11fb10e6b5752ab31fc4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to configure the DFSDM1 clock.  <br /></td></tr>
<tr class="memitem:ga5bd849cb75a56ae9a27a164e7d3c8575" id="r_ga5bd849cb75a56ae9a27a164e7d3c8575"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga5bd849cb75a56ae9a27a164e7d3c8575">__HAL_RCC_GET_DFSDM1_SOURCE</a>()</td></tr>
<tr class="memdesc:ga5bd849cb75a56ae9a27a164e7d3c8575"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the DFSDM1 clock source.  <br /></td></tr>
<tr class="memitem:ga7aff87df867beb2eb7eddbbfe06fcdc6" id="r_ga7aff87df867beb2eb7eddbbfe06fcdc6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga7aff87df867beb2eb7eddbbfe06fcdc6">__HAL_RCC_CEC_CONFIG</a>(__CECCLKSource__)</td></tr>
<tr class="memdesc:ga7aff87df867beb2eb7eddbbfe06fcdc6"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the CEC clock (CECCLK).  <br /></td></tr>
<tr class="memitem:ga7a636a5c50887bba7270924c3eb6ef2f" id="r_ga7a636a5c50887bba7270924c3eb6ef2f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga7a636a5c50887bba7270924c3eb6ef2f">__HAL_RCC_GET_CEC_SOURCE</a>()</td></tr>
<tr class="memdesc:ga7a636a5c50887bba7270924c3eb6ef2f"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the CEC clock source.  <br /></td></tr>
<tr class="memitem:gaa463f3972818967005d31114221e1cdc" id="r_gaa463f3972818967005d31114221e1cdc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaa463f3972818967005d31114221e1cdc">__HAL_RCC_CLKP_CONFIG</a>(__CLKPSource__)</td></tr>
<tr class="memdesc:gaa463f3972818967005d31114221e1cdc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to configure the CLKP : Oscillator clock for peripheral.  <br /></td></tr>
<tr class="memitem:ga5d047265ca753e28b45b09e53c3f50fe" id="r_ga5d047265ca753e28b45b09e53c3f50fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga5d047265ca753e28b45b09e53c3f50fe">__HAL_RCC_GET_CLKP_SOURCE</a>()</td></tr>
<tr class="memdesc:ga5d047265ca753e28b45b09e53c3f50fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the Oscillator clock for peripheral source.  <br /></td></tr>
<tr class="memitem:ga8da215b69bc3712d5bb359c66198d374" id="r_ga8da215b69bc3712d5bb359c66198d374"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga8da215b69bc3712d5bb359c66198d374">__HAL_RCC_SPI123_CONFIG</a>(__RCC_SPI123CLKSource__)</td></tr>
<tr class="memdesc:ga8da215b69bc3712d5bb359c66198d374"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to Configure the SPI1/2/3 clock source.  <br /></td></tr>
<tr class="memitem:ga28d7eae98ab899dc6e1d4e80b8aea33d" id="r_ga28d7eae98ab899dc6e1d4e80b8aea33d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga28d7eae98ab899dc6e1d4e80b8aea33d">__HAL_RCC_GET_SPI123_SOURCE</a>()</td></tr>
<tr class="memdesc:ga28d7eae98ab899dc6e1d4e80b8aea33d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the SPI1/2/3 clock source.  <br /></td></tr>
<tr class="memitem:ga9b531a40f565975ef8901b48afddf1cc" id="r_ga9b531a40f565975ef8901b48afddf1cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga9b531a40f565975ef8901b48afddf1cc">__HAL_RCC_SPI1_CONFIG</a>&#160;&#160;&#160;<a class="el" href="#ga8da215b69bc3712d5bb359c66198d374">__HAL_RCC_SPI123_CONFIG</a></td></tr>
<tr class="memdesc:ga9b531a40f565975ef8901b48afddf1cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to Configure the SPI1 clock source.  <br /></td></tr>
<tr class="memitem:gaa390c5d70fdb5e8c4d9171a79e3e95a1" id="r_gaa390c5d70fdb5e8c4d9171a79e3e95a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaa390c5d70fdb5e8c4d9171a79e3e95a1">__HAL_RCC_GET_SPI1_SOURCE</a>&#160;&#160;&#160;<a class="el" href="#ga28d7eae98ab899dc6e1d4e80b8aea33d">__HAL_RCC_GET_SPI123_SOURCE</a></td></tr>
<tr class="memdesc:gaa390c5d70fdb5e8c4d9171a79e3e95a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the SPI1 clock source.  <br /></td></tr>
<tr class="memitem:ga03aafcdc3a862d9f10a5d1fcce4b549e" id="r_ga03aafcdc3a862d9f10a5d1fcce4b549e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga03aafcdc3a862d9f10a5d1fcce4b549e">__HAL_RCC_SPI2_CONFIG</a>&#160;&#160;&#160;<a class="el" href="#ga8da215b69bc3712d5bb359c66198d374">__HAL_RCC_SPI123_CONFIG</a></td></tr>
<tr class="memdesc:ga03aafcdc3a862d9f10a5d1fcce4b549e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to Configure the SPI2 clock source.  <br /></td></tr>
<tr class="memitem:gaf1fd8060d50a3ca2ee9e6d193546126e" id="r_gaf1fd8060d50a3ca2ee9e6d193546126e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaf1fd8060d50a3ca2ee9e6d193546126e">__HAL_RCC_GET_SPI2_SOURCE</a>&#160;&#160;&#160;<a class="el" href="#ga28d7eae98ab899dc6e1d4e80b8aea33d">__HAL_RCC_GET_SPI123_SOURCE</a></td></tr>
<tr class="memdesc:gaf1fd8060d50a3ca2ee9e6d193546126e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the SPI2 clock source.  <br /></td></tr>
<tr class="memitem:ga72e45b0673f5829c390032f8bbb24f17" id="r_ga72e45b0673f5829c390032f8bbb24f17"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga72e45b0673f5829c390032f8bbb24f17">__HAL_RCC_SPI3_CONFIG</a>&#160;&#160;&#160;<a class="el" href="#ga8da215b69bc3712d5bb359c66198d374">__HAL_RCC_SPI123_CONFIG</a></td></tr>
<tr class="memdesc:ga72e45b0673f5829c390032f8bbb24f17"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to Configure the SPI3 clock source.  <br /></td></tr>
<tr class="memitem:ga05c66c28f3d72c123bb284e106a0d99b" id="r_ga05c66c28f3d72c123bb284e106a0d99b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga05c66c28f3d72c123bb284e106a0d99b">__HAL_RCC_GET_SPI3_SOURCE</a>&#160;&#160;&#160;<a class="el" href="#ga28d7eae98ab899dc6e1d4e80b8aea33d">__HAL_RCC_GET_SPI123_SOURCE</a></td></tr>
<tr class="memdesc:ga05c66c28f3d72c123bb284e106a0d99b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the SPI3 clock source.  <br /></td></tr>
<tr class="memitem:gaecfe51f0d81f0130e1a5a06408320b72" id="r_gaecfe51f0d81f0130e1a5a06408320b72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaecfe51f0d81f0130e1a5a06408320b72">__HAL_RCC_SPI45_CONFIG</a>(__RCC_SPI45CLKSource__)</td></tr>
<tr class="memdesc:gaecfe51f0d81f0130e1a5a06408320b72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to Configure the SPI4/5 clock source.  <br /></td></tr>
<tr class="memitem:gafdcff08fc3544c712d1f4d2d17994842" id="r_gafdcff08fc3544c712d1f4d2d17994842"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gafdcff08fc3544c712d1f4d2d17994842">__HAL_RCC_GET_SPI45_SOURCE</a>()</td></tr>
<tr class="memdesc:gafdcff08fc3544c712d1f4d2d17994842"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the SPI4/5 clock source.  <br /></td></tr>
<tr class="memitem:ga04806afde06b2bc3b4e409b81fce5c41" id="r_ga04806afde06b2bc3b4e409b81fce5c41"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga04806afde06b2bc3b4e409b81fce5c41">__HAL_RCC_SPI4_CONFIG</a>&#160;&#160;&#160;<a class="el" href="#gaecfe51f0d81f0130e1a5a06408320b72">__HAL_RCC_SPI45_CONFIG</a></td></tr>
<tr class="memdesc:ga04806afde06b2bc3b4e409b81fce5c41"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to Configure the SPI4 clock source.  <br /></td></tr>
<tr class="memitem:gaffce7a01f11a975120059a0a2a322d01" id="r_gaffce7a01f11a975120059a0a2a322d01"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaffce7a01f11a975120059a0a2a322d01">__HAL_RCC_GET_SPI4_SOURCE</a>&#160;&#160;&#160;<a class="el" href="#gafdcff08fc3544c712d1f4d2d17994842">__HAL_RCC_GET_SPI45_SOURCE</a></td></tr>
<tr class="memdesc:gaffce7a01f11a975120059a0a2a322d01"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the SPI4 clock source.  <br /></td></tr>
<tr class="memitem:ga14c138363b18bdee29cbb3ec82594b92" id="r_ga14c138363b18bdee29cbb3ec82594b92"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga14c138363b18bdee29cbb3ec82594b92">__HAL_RCC_SPI5_CONFIG</a>&#160;&#160;&#160;<a class="el" href="#gaecfe51f0d81f0130e1a5a06408320b72">__HAL_RCC_SPI45_CONFIG</a></td></tr>
<tr class="memdesc:ga14c138363b18bdee29cbb3ec82594b92"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to Configure the SPI5 clock source.  <br /></td></tr>
<tr class="memitem:ga8ad4e833262fabd7960aab8946928a5f" id="r_ga8ad4e833262fabd7960aab8946928a5f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga8ad4e833262fabd7960aab8946928a5f">__HAL_RCC_GET_SPI5_SOURCE</a>&#160;&#160;&#160;<a class="el" href="#gafdcff08fc3544c712d1f4d2d17994842">__HAL_RCC_GET_SPI45_SOURCE</a></td></tr>
<tr class="memdesc:ga8ad4e833262fabd7960aab8946928a5f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the SPI5 clock source.  <br /></td></tr>
<tr class="memitem:ga1170019b0ed2e1301d2284c2af149f33" id="r_ga1170019b0ed2e1301d2284c2af149f33"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga1170019b0ed2e1301d2284c2af149f33">__HAL_RCC_SPI6_CONFIG</a>(__RCC_SPI6CLKSource__)</td></tr>
<tr class="memdesc:ga1170019b0ed2e1301d2284c2af149f33"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to Configure the SPI6 clock source.  <br /></td></tr>
<tr class="memitem:ga8e7af9e242f90f474d245e72066e163f" id="r_ga8e7af9e242f90f474d245e72066e163f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga8e7af9e242f90f474d245e72066e163f">__HAL_RCC_GET_SPI6_SOURCE</a>()</td></tr>
<tr class="memdesc:ga8e7af9e242f90f474d245e72066e163f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the SPI6 clock source.  <br /></td></tr>
<tr class="memitem:ga7754edd5cc00e691c5007f22d3a93d38" id="r_ga7754edd5cc00e691c5007f22d3a93d38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga7754edd5cc00e691c5007f22d3a93d38">__HAL_RCC_SDMMC_CONFIG</a>(__SDMMCCLKSource__)</td></tr>
<tr class="memdesc:ga7754edd5cc00e691c5007f22d3a93d38"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to configure the SDMMC clock.  <br /></td></tr>
<tr class="memitem:gacccdca63ee93770444eaab77cd831c75" id="r_gacccdca63ee93770444eaab77cd831c75"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gacccdca63ee93770444eaab77cd831c75">__HAL_RCC_GET_SDMMC_SOURCE</a>()</td></tr>
<tr class="memdesc:gacccdca63ee93770444eaab77cd831c75"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to get the SDMMC clock.  <br /></td></tr>
<tr class="memitem:gae34a5e47c3e3a519bfca1f4313a88f9f" id="r_gae34a5e47c3e3a519bfca1f4313a88f9f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gae34a5e47c3e3a519bfca1f4313a88f9f">__HAL_RCC_RNG_CONFIG</a>(__RNGCLKSource__)</td></tr>
<tr class="memdesc:gae34a5e47c3e3a519bfca1f4313a88f9f"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to configure the RNG clock (RNGCLK).  <br /></td></tr>
<tr class="memitem:gad8f27c485f7252991877f8e423b73d46" id="r_gad8f27c485f7252991877f8e423b73d46"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gad8f27c485f7252991877f8e423b73d46">__HAL_RCC_GET_RNG_SOURCE</a>()</td></tr>
<tr class="memdesc:gad8f27c485f7252991877f8e423b73d46"><td class="mdescLeft">&#160;</td><td class="mdescRight">macro to get the RNG clock source.  <br /></td></tr>
<tr class="memitem:ga292ca7c84f192778314125ed6d7c8333" id="r_ga292ca7c84f192778314125ed6d7c8333"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga292ca7c84f192778314125ed6d7c8333">__HAL_RCC_TIMCLKPRESCALER</a>(__PRESC__)</td></tr>
<tr class="memdesc:ga292ca7c84f192778314125ed6d7c8333"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to configure the Timers clocks prescalers.  <br /></td></tr>
<tr class="memitem:gafca78bb6fbfed8a31ef7ee030d424b50" id="r_gafca78bb6fbfed8a31ef7ee030d424b50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gafca78bb6fbfed8a31ef7ee030d424b50">__HAL_RCC_LSECSS_EXTI_ENABLE_IT</a>()</td></tr>
<tr class="memdesc:gafca78bb6fbfed8a31ef7ee030d424b50"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the RCC LSE CSS Extended Interrupt Line.  <br /></td></tr>
<tr class="memitem:gaa5c2a31f367b8085be517e315b8c0196" id="r_gaa5c2a31f367b8085be517e315b8c0196"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaa5c2a31f367b8085be517e315b8c0196">__HAL_RCC_LSECSS_EXTI_DISABLE_IT</a>()</td></tr>
<tr class="memdesc:gaa5c2a31f367b8085be517e315b8c0196"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the RCC LSE CSS Extended Interrupt Line.  <br /></td></tr>
<tr class="memitem:gad5f8173d2752512c30375c9ca7890fbc" id="r_gad5f8173d2752512c30375c9ca7890fbc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gad5f8173d2752512c30375c9ca7890fbc">__HAL_RCC_LSECSS_EXTI_ENABLE_EVENT</a>()</td></tr>
<tr class="memdesc:gad5f8173d2752512c30375c9ca7890fbc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the RCC LSE CSS Event Line.  <br /></td></tr>
<tr class="memitem:ga20711e52b237c9c598c87d5329a9700f" id="r_ga20711e52b237c9c598c87d5329a9700f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga20711e52b237c9c598c87d5329a9700f">__HAL_RCC_LSECSS_EXTI_DISABLE_EVENT</a>()</td></tr>
<tr class="memdesc:ga20711e52b237c9c598c87d5329a9700f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the RCC LSE CSS Event Line.  <br /></td></tr>
<tr class="memitem:ga45a0bf105427b24b377125346b2e597d" id="r_ga45a0bf105427b24b377125346b2e597d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga45a0bf105427b24b377125346b2e597d">__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE</a>()</td></tr>
<tr class="memdesc:ga45a0bf105427b24b377125346b2e597d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the RCC LSE CSS Extended Interrupt Falling Trigger.  <br /></td></tr>
<tr class="memitem:ga5b8a28d3896b67495b996d001084885e" id="r_ga5b8a28d3896b67495b996d001084885e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga5b8a28d3896b67495b996d001084885e">__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE</a>()</td></tr>
<tr class="memdesc:ga5b8a28d3896b67495b996d001084885e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the RCC LSE CSS Extended Interrupt Falling Trigger.  <br /></td></tr>
<tr class="memitem:ga14487ed9c109cb494cae4a9762b7c294" id="r_ga14487ed9c109cb494cae4a9762b7c294"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga14487ed9c109cb494cae4a9762b7c294">__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE</a>()</td></tr>
<tr class="memdesc:ga14487ed9c109cb494cae4a9762b7c294"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the RCC LSE CSS Extended Interrupt Rising Trigger.  <br /></td></tr>
<tr class="memitem:ga2746b06cbf0f080a600f3f895c95f3fb" id="r_ga2746b06cbf0f080a600f3f895c95f3fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga2746b06cbf0f080a600f3f895c95f3fb">__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE</a>()</td></tr>
<tr class="memdesc:ga2746b06cbf0f080a600f3f895c95f3fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the RCC LSE CSS Extended Interrupt Rising Trigger.  <br /></td></tr>
<tr class="memitem:ga075e9194bfc08b5da32af130a74e7cb4" id="r_ga075e9194bfc08b5da32af130a74e7cb4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga075e9194bfc08b5da32af130a74e7cb4">__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE</a>()</td></tr>
<tr class="memdesc:ga075e9194bfc08b5da32af130a74e7cb4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the RCC LSE CSS Extended Interrupt Rising &amp; Falling Trigger.  <br /></td></tr>
<tr class="memitem:gacea34070069d535080039e3067aba82d" id="r_gacea34070069d535080039e3067aba82d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gacea34070069d535080039e3067aba82d">__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE</a>()</td></tr>
<tr class="memdesc:gacea34070069d535080039e3067aba82d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the RCC LSE CSS Extended Interrupt Rising &amp; Falling Trigger.  <br /></td></tr>
<tr class="memitem:ga65fa248e1dd8c7258a50ba03c4e2ff85" id="r_ga65fa248e1dd8c7258a50ba03c4e2ff85"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga65fa248e1dd8c7258a50ba03c4e2ff85">__HAL_RCC_LSECSS_EXTI_GET_FLAG</a>()</td></tr>
<tr class="memdesc:ga65fa248e1dd8c7258a50ba03c4e2ff85"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.  <br /></td></tr>
<tr class="memitem:ga6171e2da4b75a993142330025862864f" id="r_ga6171e2da4b75a993142330025862864f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga6171e2da4b75a993142330025862864f">__HAL_RCC_LSECSS_EXTI_CLEAR_FLAG</a>()</td></tr>
<tr class="memdesc:ga6171e2da4b75a993142330025862864f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the RCC LSE CSS EXTI flag.  <br /></td></tr>
<tr class="memitem:gac5a7ed26daae142eb6cce551728ee88c" id="r_gac5a7ed26daae142eb6cce551728ee88c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gac5a7ed26daae142eb6cce551728ee88c">__HAL_RCC_LSECSS_EXTI_GENERATE_SWIT</a>()</td></tr>
<tr class="memdesc:gac5a7ed26daae142eb6cce551728ee88c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Generate a Software interrupt on the RCC LSE CSS EXTI line.  <br /></td></tr>
<tr class="memitem:gae7a58e5b7b665d6fdd5af5f444d8ca8a" id="r_gae7a58e5b7b665d6fdd5af5f444d8ca8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gae7a58e5b7b665d6fdd5af5f444d8ca8a">__HAL_RCC_CRS_ENABLE_IT</a>(__INTERRUPT__)</td></tr>
<tr class="memdesc:gae7a58e5b7b665d6fdd5af5f444d8ca8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the specified CRS interrupts.  <br /></td></tr>
<tr class="memitem:ga83218d96e4d75af9508a18cb81ad1254" id="r_ga83218d96e4d75af9508a18cb81ad1254"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga83218d96e4d75af9508a18cb81ad1254">__HAL_RCC_CRS_DISABLE_IT</a>(__INTERRUPT__)</td></tr>
<tr class="memdesc:ga83218d96e4d75af9508a18cb81ad1254"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the specified CRS interrupts.  <br /></td></tr>
<tr class="memitem:ga86642491c37c596d1c07699030d40d48" id="r_ga86642491c37c596d1c07699030d40d48"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga86642491c37c596d1c07699030d40d48">__HAL_RCC_CRS_GET_IT_SOURCE</a>(__INTERRUPT__)</td></tr>
<tr class="memdesc:ga86642491c37c596d1c07699030d40d48"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check whether the CRS interrupt has occurred or not.  <br /></td></tr>
<tr class="memitem:ga4c5b57880a8c7e917998d0c6a73351fb" id="r_ga4c5b57880a8c7e917998d0c6a73351fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga4c5b57880a8c7e917998d0c6a73351fb">RCC_CRS_IT_ERROR_MASK</a>&#160;&#160;&#160;((uint32_t)(<a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga031f913312b8af1f38dc7c5adcd716f1">RCC_CRS_IT_TRIMOVF</a> | <a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#gaf464654bbdfda5b86982fc4aa5b5a031">RCC_CRS_IT_SYNCERR</a> | <a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#gac6b25a96e779b2f7ee3223101109ee33">RCC_CRS_IT_SYNCMISS</a>))</td></tr>
<tr class="memdesc:ga4c5b57880a8c7e917998d0c6a73351fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the CRS interrupt pending bits.  <br /></td></tr>
<tr class="memitem:ga8f7ada1acec652afe441dfc4515e18be" id="r_ga8f7ada1acec652afe441dfc4515e18be"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga8f7ada1acec652afe441dfc4515e18be">__HAL_RCC_CRS_CLEAR_IT</a>(__INTERRUPT__)</td></tr>
<tr class="memitem:gad40507a114061cddd85528ecc7555e1b" id="r_gad40507a114061cddd85528ecc7555e1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gad40507a114061cddd85528ecc7555e1b">__HAL_RCC_CRS_GET_FLAG</a>(__FLAG__)</td></tr>
<tr class="memdesc:gad40507a114061cddd85528ecc7555e1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check whether the specified CRS flag is set or not.  <br /></td></tr>
<tr class="memitem:ga39626ad9573958c96dccc66d13b1b6fe" id="r_ga39626ad9573958c96dccc66d13b1b6fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga39626ad9573958c96dccc66d13b1b6fe">RCC_CRS_FLAG_ERROR_MASK</a>&#160;&#160;&#160;((uint32_t)(<a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga4c4c324494f9c6469e53d225242c73d4">RCC_CRS_FLAG_TRIMOVF</a> | <a class="el" href="group___r_c_c_ex___c_r_s___flags.html#gad49f59e34225920835b69a34f1b4c02b">RCC_CRS_FLAG_SYNCERR</a> | <a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga78549e9f343ad843d6e5d45b4e08433c">RCC_CRS_FLAG_SYNCMISS</a>))</td></tr>
<tr class="memdesc:ga39626ad9573958c96dccc66d13b1b6fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the CRS specified FLAG.  <br /></td></tr>
<tr class="memitem:gaf8b5160a2401847e5b9410c9a01e5922" id="r_gaf8b5160a2401847e5b9410c9a01e5922"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaf8b5160a2401847e5b9410c9a01e5922">__HAL_RCC_CRS_CLEAR_FLAG</a>(__FLAG__)</td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<a name="doc-define-members" id="doc-define-members"></a><h2 id="header-doc-define-members" class="groupheader">Macro Definition Documentation</h2>
<a id="ga03642b548896f327c3efc876aff4b349" name="ga03642b548896f327c3efc876aff4b349"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga03642b548896f327c3efc876aff4b349">&#9670;&#160;</a></span>__HAL_RCC_ADC_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_ADC_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__ADCCLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))</div>
</div><!-- fragment -->
<p>Macro to configure the ADC clock. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__ADCCLKSource__</td><td>specifies the ADC digital interface clock source. This parameter can be one of the following values: <ul>
<li>RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock </li>
<li>RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock </li>
<li>RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="ga7aff87df867beb2eb7eddbbfe06fcdc6" name="ga7aff87df867beb2eb7eddbbfe06fcdc6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7aff87df867beb2eb7eddbbfe06fcdc6">&#9670;&#160;</a></span>__HAL_RCC_CEC_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_CEC_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__CECCLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))</div>
</div><!-- fragment -->
<p>macro to configure the CEC clock (CECCLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__CECCLKSource__</td><td>specifies the CEC clock source. This parameter can be one of the following values: <ul>
<li>RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock </li>
<li>RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock </li>
<li>RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="gaa463f3972818967005d31114221e1cdc" name="gaa463f3972818967005d31114221e1cdc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa463f3972818967005d31114221e1cdc">&#9670;&#160;</a></span>__HAL_RCC_CLKP_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_CLKP_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__CLKPSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))</div>
</div><!-- fragment -->
<p>Macro to configure the CLKP : Oscillator clock for peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__CLKPSource__</td><td>specifies Oscillator clock for peripheral This parameter can be one of the following values: <ul>
<li>RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral </li>
<li>RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral </li>
<li>RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="gaf8b5160a2401847e5b9410c9a01e5922" name="gaf8b5160a2401847e5b9410c9a01e5922"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf8b5160a2401847e5b9410c9a01e5922">&#9670;&#160;</a></span>__HAL_RCC_CRS_CLEAR_FLAG</h2>

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          <td class="memname">#define __HAL_RCC_CRS_CLEAR_FLAG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__FLAG__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                                                 <span class="keywordflow">do</span> { \</div>
<div class="line">                                                 if(((__FLAG__) &amp; <a class="code hl_define" href="#ga39626ad9573958c96dccc66d13b1b6fe">RCC_CRS_FLAG_ERROR_MASK</a>) != 0U) \</div>
<div class="line">                                                 { \</div>
<div class="line">                                                   WRITE_REG(CRS-&gt;ICR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae67dc4a9e576468b0c322902c7c47793">CRS_ICR_ERRC</a> | ((__FLAG__) &amp; ~<a class="code hl_define" href="#ga39626ad9573958c96dccc66d13b1b6fe">RCC_CRS_FLAG_ERROR_MASK</a>)); \</div>
<div class="line">                                                 } \</div>
<div class="line">                                                 <span class="keywordflow">else</span> \</div>
<div class="line">                                                 { \</div>
<div class="line">                                                   WRITE_REG(CRS-&gt;ICR, (__FLAG__)); \</div>
<div class="line">                                                 } \</div>
<div class="line">                                               } <span class="keywordflow">while</span>(0)</div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gae67dc4a9e576468b0c322902c7c47793"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gae67dc4a9e576468b0c322902c7c47793">CRS_ICR_ERRC</a></div><div class="ttdeci">#define CRS_ICR_ERRC</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:5897</div></div>
<div class="ttc" id="agroup___r_c_c_ex___exported___macros_html_ga39626ad9573958c96dccc66d13b1b6fe"><div class="ttname"><a href="#ga39626ad9573958c96dccc66d13b1b6fe">RCC_CRS_FLAG_ERROR_MASK</a></div><div class="ttdeci">#define RCC_CRS_FLAG_ERROR_MASK</div><div class="ttdoc">Clear the CRS specified FLAG.</div><div class="ttdef"><b>Definition</b> stm32h7xx_hal_rcc_ex.h:3828</div></div>
</div><!-- fragment -->
</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga8f7ada1acec652afe441dfc4515e18be">&#9670;&#160;</a></span>__HAL_RCC_CRS_CLEAR_IT</h2>

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          <td class="memname">#define __HAL_RCC_CRS_CLEAR_IT</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__INTERRUPT__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                                                 <span class="keywordflow">do</span> { \</div>
<div class="line">                                                 if(((__INTERRUPT__) &amp; <a class="code hl_define" href="#ga4c5b57880a8c7e917998d0c6a73351fb">RCC_CRS_IT_ERROR_MASK</a>) != 0U) \</div>
<div class="line">                                                 { \</div>
<div class="line">                                                   WRITE_REG(CRS-&gt;ICR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae67dc4a9e576468b0c322902c7c47793">CRS_ICR_ERRC</a> | ((__INTERRUPT__) &amp; ~<a class="code hl_define" href="#ga4c5b57880a8c7e917998d0c6a73351fb">RCC_CRS_IT_ERROR_MASK</a>)); \</div>
<div class="line">                                                 } \</div>
<div class="line">                                                 <span class="keywordflow">else</span> \</div>
<div class="line">                                                 { \</div>
<div class="line">                                                   WRITE_REG(CRS-&gt;ICR, (__INTERRUPT__)); \</div>
<div class="line">                                                 } \</div>
<div class="line">                                               } <span class="keywordflow">while</span>(0)</div>
<div class="ttc" id="agroup___r_c_c_ex___exported___macros_html_ga4c5b57880a8c7e917998d0c6a73351fb"><div class="ttname"><a href="#ga4c5b57880a8c7e917998d0c6a73351fb">RCC_CRS_IT_ERROR_MASK</a></div><div class="ttdeci">#define RCC_CRS_IT_ERROR_MASK</div><div class="ttdoc">Clear the CRS interrupt pending bits.</div><div class="ttdef"><b>Definition</b> stm32h7xx_hal_rcc_ex.h:3784</div></div>
</div><!-- fragment -->
</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga83218d96e4d75af9508a18cb81ad1254">&#9670;&#160;</a></span>__HAL_RCC_CRS_DISABLE_IT</h2>

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          <td class="memname">#define __HAL_RCC_CRS_DISABLE_IT</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__INTERRUPT__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">CLEAR_BIT(CRS-&gt;CR, (__INTERRUPT__))</div>
</div><!-- fragment -->
<p>Disable the specified CRS interrupts. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__INTERRUPT__</td><td>specifies the CRS interrupt sources to be disabled. This parameter can be any combination of the following values: <ul>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga772a7eb77eaea0622fb3e3b20275a37f">RCC_CRS_IT_SYNCOK</a> SYNC event OK interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga8b9e2cbfa3fd8d7c18f81685c24a394f">RCC_CRS_IT_SYNCWARN</a> SYNC warning interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga01a198f277ff33e6fd5a9c2a6ad908b9">RCC_CRS_IT_ERR</a> Synchronization or trimming error interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#gadf2de3907d21dfaea6b2444d66adfe13">RCC_CRS_IT_ESYNC</a> Expected SYNC interrupt </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gae7a58e5b7b665d6fdd5af5f444d8ca8a">&#9670;&#160;</a></span>__HAL_RCC_CRS_ENABLE_IT</h2>

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          <td class="memname">#define __HAL_RCC_CRS_ENABLE_IT</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__INTERRUPT__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">SET_BIT(CRS-&gt;CR, (__INTERRUPT__))</div>
</div><!-- fragment -->
<p>Enable the specified CRS interrupts. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__INTERRUPT__</td><td>specifies the CRS interrupt sources to be enabled. This parameter can be any combination of the following values: <ul>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga772a7eb77eaea0622fb3e3b20275a37f">RCC_CRS_IT_SYNCOK</a> SYNC event OK interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga8b9e2cbfa3fd8d7c18f81685c24a394f">RCC_CRS_IT_SYNCWARN</a> SYNC warning interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga01a198f277ff33e6fd5a9c2a6ad908b9">RCC_CRS_IT_ERR</a> Synchronization or trimming error interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#gadf2de3907d21dfaea6b2444d66adfe13">RCC_CRS_IT_ESYNC</a> Expected SYNC interrupt </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gad40507a114061cddd85528ecc7555e1b">&#9670;&#160;</a></span>__HAL_RCC_CRS_GET_FLAG</h2>

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        <tr>
          <td class="memname">#define __HAL_RCC_CRS_GET_FLAG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__FLAG__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(READ_BIT(CRS-&gt;ISR, (__FLAG__)) == (__FLAG__))</div>
</div><!-- fragment -->
<p>Check whether the specified CRS flag is set or not. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__FLAG__</td><td>specifies the flag to check. This parameter can be one of the following values: <ul>
<li><a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga27e1ae14c7854ca42faf5379bea5ac39">RCC_CRS_FLAG_SYNCOK</a> SYNC event OK </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga244c3ca47b8099a79212ab10d8e823c9">RCC_CRS_FLAG_SYNCWARN</a> SYNC warning </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga92be7705ece62c427a262355305527fa">RCC_CRS_FLAG_ERR</a> Error </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga10697d7c12b710c52c26db522c11986b">RCC_CRS_FLAG_ESYNC</a> Expected SYNC </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga4c4c324494f9c6469e53d225242c73d4">RCC_CRS_FLAG_TRIMOVF</a> Trimming overflow or underflow </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___flags.html#gad49f59e34225920835b69a34f1b4c02b">RCC_CRS_FLAG_SYNCERR</a> SYNC error </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga78549e9f343ad843d6e5d45b4e08433c">RCC_CRS_FLAG_SYNCMISS</a> SYNC missed </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>new state of <em>FLAG</em> (TRUE or FALSE). </td></tr>
  </table>
  </dd>
</dl>

</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga86642491c37c596d1c07699030d40d48">&#9670;&#160;</a></span>__HAL_RCC_CRS_GET_IT_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_CRS_GET_IT_SOURCE</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__INTERRUPT__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((READ_BIT(CRS-&gt;CR, (__INTERRUPT__)) != 0U) ? SET : RESET)</div>
</div><!-- fragment -->
<p>Check whether the CRS interrupt has occurred or not. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__INTERRUPT__</td><td>specifies the CRS interrupt source to check. This parameter can be one of the following values: <ul>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga772a7eb77eaea0622fb3e3b20275a37f">RCC_CRS_IT_SYNCOK</a> SYNC event OK interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga8b9e2cbfa3fd8d7c18f81685c24a394f">RCC_CRS_IT_SYNCWARN</a> SYNC warning interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga01a198f277ff33e6fd5a9c2a6ad908b9">RCC_CRS_IT_ERR</a> Synchronization or trimming error interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#gadf2de3907d21dfaea6b2444d66adfe13">RCC_CRS_IT_ESYNC</a> Expected SYNC interrupt </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>new state of <b>INTERRUPT</b> (SET or RESET). </td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga79c4e732154d11fb10e6b5752ab31fc4">&#9670;&#160;</a></span>__HAL_RCC_DFSDM1_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_DFSDM1_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__DFSDM1CLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))</div>
</div><!-- fragment -->
<p>Macro to configure the DFSDM1 clock. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__DFSDM1CLKSource__</td><td>specifies the DFSDM1 clock source. This parameter can be one of the following values: <ul>
<li>RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock </li>
<li>RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga18a22f0e5f811ba9fee8bb2906dfa60b">&#9670;&#160;</a></span>__HAL_RCC_FMC_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_FMC_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__FMCCLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))</div>
</div><!-- fragment -->
<p>macro to configure the FMC clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__FMCCLKSource__</td><td>specifies the FMC clock source. <ul>
<li>RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock </li>
<li>RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock </li>
<li>RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock </li>
<li>RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga2ee9f1838a8450f949b548a06ed3bc58">&#9670;&#160;</a></span>__HAL_RCC_GET_ADC_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_ADC_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))</div>
</div><!-- fragment -->
<p>Macro to get the ADC clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock </li>
<li>RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock </li>
<li>RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga7a636a5c50887bba7270924c3eb6ef2f">&#9670;&#160;</a></span>__HAL_RCC_GET_CEC_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_CEC_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;CDCCIP2R, RCC_CDCCIP2R_CECSEL)))</div>
</div><!-- fragment -->
<p>macro to get the CEC clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock </li>
<li>RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock </li>
<li>RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga5d047265ca753e28b45b09e53c3f50fe">&#9670;&#160;</a></span>__HAL_RCC_GET_CLKP_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_CLKP_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;CDCCIPR, RCC_CDCCIPR_CKPERSEL)))</div>
</div><!-- fragment -->
<p>Macro to get the Oscillator clock for peripheral source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral </li>
<li>RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral </li>
<li>RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga5bd849cb75a56ae9a27a164e7d3c8575">&#9670;&#160;</a></span>__HAL_RCC_GET_DFSDM1_SOURCE</h2>

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        <tr>
          <td class="memname">#define __HAL_RCC_GET_DFSDM1_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))</div>
</div><!-- fragment -->
<p>Macro to get the DFSDM1 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock </li>
<li>RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga48733b3d8faeb67777184a503bbbf2fa">&#9670;&#160;</a></span>__HAL_RCC_GET_FMC_SOURCE</h2>

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        <tr>
          <td class="memname">#define __HAL_RCC_GET_FMC_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;CDCCIPR, RCC_CDCCIPR_FMCSEL)))</div>
</div><!-- fragment -->
<p>macro to get the FMC clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock </li>
<li>RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock </li>
<li>RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock </li>
<li>RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga18d44d4471dc6940cdfa9ee4ad4025d3">&#9670;&#160;</a></span>__HAL_RCC_GET_I2C1235_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_I2C1235_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL)))</div>
</div><!-- fragment -->
<p>macro to get the I2C1/2/3/5* clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock </li>
<li>RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock </li>
<li>RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock </li>
<li>RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock</li>
</ul>
(**): Available on stm32h72xxx and stm32h73xxx family lines. </td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gabc9e99366b5dfab7a6c535f8f48af8d3">&#9670;&#160;</a></span>__HAL_RCC_GET_I2C1_SOURCE</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_GET_I2C1_SOURCE&#160;&#160;&#160;__HAL_RCC_GET_I2C123_SOURCE</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to get the I2C1 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock </li>
<li>RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock </li>
<li>RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock </li>
<li>RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gabaa32df2434beb7a446be4aba5c2a06b">&#9670;&#160;</a></span>__HAL_RCC_GET_I2C2_SOURCE</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_GET_I2C2_SOURCE&#160;&#160;&#160;__HAL_RCC_GET_I2C123_SOURCE</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to get the I2C2 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock </li>
<li>RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock </li>
<li>RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock </li>
<li>RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga06f70ebfa24caeb198001d5c02d6dc78">&#9670;&#160;</a></span>__HAL_RCC_GET_I2C3_SOURCE</h2>

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        <tr>
          <td class="memname">#define __HAL_RCC_GET_I2C3_SOURCE&#160;&#160;&#160;__HAL_RCC_GET_I2C123_SOURCE</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to get the I2C3 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock </li>
<li>RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock </li>
<li>RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock </li>
<li>RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga6632a1fbc809f6f6dedde0d36cbaa3c9">&#9670;&#160;</a></span>__HAL_RCC_GET_I2C4_SOURCE</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_GET_I2C4_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;SRDCCIPR, RCC_SRDCCIPR_I2C4SEL)))</div>
</div><!-- fragment -->
<p>macro to get the I2C4 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock </li>
<li>RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock </li>
<li>RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock </li>
<li>RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gad6688c07a2a8c314df547de8caf378bb">&#9670;&#160;</a></span>__HAL_RCC_GET_LPTIM1_SOURCE</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_GET_LPTIM1_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))</div>
</div><!-- fragment -->
<p>macro to get the LPTIM1 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock </li>
<li>RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock </li>
<li>RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock </li>
<li>RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock </li>
<li>RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock </li>
<li>RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga806f1d6e6a7d741b4d0524aa849f8ed8">&#9670;&#160;</a></span>__HAL_RCC_GET_LPTIM2_SOURCE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_GET_LPTIM2_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))</div>
</div><!-- fragment -->
<p>macro to get the LPTIM2 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock </li>
<li>RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock </li>
<li>RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock </li>
<li>RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock </li>
<li>RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock </li>
<li>RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga6b2263ea1e054aee45c85e64dcfeb99f">&#9670;&#160;</a></span>__HAL_RCC_GET_LPTIM345_SOURCE</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_GET_LPTIM345_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))</div>
</div><!-- fragment -->
<p>macro to get the LPTIM3/4/5 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock </li>
<li>RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock </li>
<li>RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock </li>
<li>RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock </li>
<li>RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock </li>
<li>RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga08d9d85cee6e2656f7a7b0cf920326b8">&#9670;&#160;</a></span>__HAL_RCC_GET_LPTIM3_SOURCE</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_GET_LPTIM3_SOURCE&#160;&#160;&#160;<a class="el" href="#ga6b2263ea1e054aee45c85e64dcfeb99f">__HAL_RCC_GET_LPTIM345_SOURCE</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to get the LPTIM3 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock </li>
<li>RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock </li>
<li>RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock </li>
<li>RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock </li>
<li>RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock </li>
<li>RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga193015f4df5fb541bd4fbbc20d1e20ae">&#9670;&#160;</a></span>__HAL_RCC_GET_LPUART1_SOURCE</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_GET_LPUART1_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))</div>
</div><!-- fragment -->
<p>macro to get the LPUART1 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock </li>
<li>RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock </li>
<li>RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock </li>
<li>RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock </li>
<li>RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock </li>
<li>RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gad8f27c485f7252991877f8e423b73d46">&#9670;&#160;</a></span>__HAL_RCC_GET_RNG_SOURCE</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_GET_RNG_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))</div>
</div><!-- fragment -->
<p>macro to get the RNG clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock </li>
<li>RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock </li>
<li>RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock </li>
<li>RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga9af45dae7c2f2f1c8848be68d7bded7e">&#9670;&#160;</a></span>__HAL_RCC_GET_SAI1_SOURCE</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_GET_SAI1_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))</div>
</div><!-- fragment -->
<p>Macro to get the SAI1 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL </li>
<li>RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 </li>
<li>RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 </li>
<li>RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP </li>
<li>RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="gacccdca63ee93770444eaab77cd831c75" name="gacccdca63ee93770444eaab77cd831c75"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gacccdca63ee93770444eaab77cd831c75">&#9670;&#160;</a></span>__HAL_RCC_GET_SDMMC_SOURCE</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_GET_SDMMC_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))</div>
</div><!-- fragment -->
<p>Macro to get the SDMMC clock. </p>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gad3ddc626288e3b401da0b8547f2ac0d3">&#9670;&#160;</a></span>__HAL_RCC_GET_SPDIFRX_SOURCE</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_GET_SPDIFRX_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))</div>
</div><!-- fragment -->
<p>Macro to get the SPDIFRX clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga28d7eae98ab899dc6e1d4e80b8aea33d">&#9670;&#160;</a></span>__HAL_RCC_GET_SPI123_SOURCE</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_GET_SPI123_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))</div>
</div><!-- fragment -->
<p>Macro to get the SPI1/2/3 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL </li>
<li>RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 </li>
<li>RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 </li>
<li>RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP </li>
<li>RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gaa390c5d70fdb5e8c4d9171a79e3e95a1">&#9670;&#160;</a></span>__HAL_RCC_GET_SPI1_SOURCE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_GET_SPI1_SOURCE&#160;&#160;&#160;<a class="el" href="#ga28d7eae98ab899dc6e1d4e80b8aea33d">__HAL_RCC_GET_SPI123_SOURCE</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Macro to get the SPI1 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL </li>
<li>RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 </li>
<li>RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 </li>
<li>RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP </li>
<li>RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gaf1fd8060d50a3ca2ee9e6d193546126e">&#9670;&#160;</a></span>__HAL_RCC_GET_SPI2_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_SPI2_SOURCE&#160;&#160;&#160;<a class="el" href="#ga28d7eae98ab899dc6e1d4e80b8aea33d">__HAL_RCC_GET_SPI123_SOURCE</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Macro to get the SPI2 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL </li>
<li>RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 </li>
<li>RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 </li>
<li>RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP </li>
<li>RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga05c66c28f3d72c123bb284e106a0d99b">&#9670;&#160;</a></span>__HAL_RCC_GET_SPI3_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_SPI3_SOURCE&#160;&#160;&#160;<a class="el" href="#ga28d7eae98ab899dc6e1d4e80b8aea33d">__HAL_RCC_GET_SPI123_SOURCE</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Macro to get the SPI3 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL </li>
<li>RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 </li>
<li>RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 </li>
<li>RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP </li>
<li>RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gafdcff08fc3544c712d1f4d2d17994842">&#9670;&#160;</a></span>__HAL_RCC_GET_SPI45_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_SPI45_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))</div>
</div><!-- fragment -->
<p>Macro to get the SPI4/5 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2 </li>
<li>RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 </li>
<li>RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 </li>
<li>RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI </li>
<li>RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI </li>
<li>RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gaffce7a01f11a975120059a0a2a322d01">&#9670;&#160;</a></span>__HAL_RCC_GET_SPI4_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_SPI4_SOURCE&#160;&#160;&#160;<a class="el" href="#gafdcff08fc3544c712d1f4d2d17994842">__HAL_RCC_GET_SPI45_SOURCE</a></td>
        </tr>
      </table>
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<p>Macro to get the SPI4 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2 </li>
<li>RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 </li>
<li>RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 </li>
<li>RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI </li>
<li>RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI </li>
<li>RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga8ad4e833262fabd7960aab8946928a5f">&#9670;&#160;</a></span>__HAL_RCC_GET_SPI5_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_SPI5_SOURCE&#160;&#160;&#160;<a class="el" href="#gafdcff08fc3544c712d1f4d2d17994842">__HAL_RCC_GET_SPI45_SOURCE</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Macro to get the SPI5 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2 </li>
<li>RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 </li>
<li>RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 </li>
<li>RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI </li>
<li>RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI </li>
<li>RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga8e7af9e242f90f474d245e72066e163f">&#9670;&#160;</a></span>__HAL_RCC_GET_SPI6_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_SPI6_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))</div>
</div><!-- fragment -->
<p>Macro to get the SPI6 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 </li>
<li>RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 </li>
<li>RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 </li>
<li>RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI </li>
<li>RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI </li>
<li>RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE </li>
<li>RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga3ddf343654e802758b5e779d81122404">&#9670;&#160;</a></span>__HAL_RCC_GET_SWPMI1_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_SWPMI1_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))</div>
</div><!-- fragment -->
<p>Macro to get the SWPMI1 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock </li>
<li>RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga9945c36dd4ffce9d8c1b213e56edf80a">&#9670;&#160;</a></span>__HAL_RCC_GET_UART4_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_UART4_SOURCE&#160;&#160;&#160;<a class="el" href="#ga2de2c847f3e490a5b6ac8b1d13b66883">__HAL_RCC_GET_USART234578_SOURCE</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to get the UART4 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock </li>
<li>RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock </li>
<li>RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock </li>
<li>RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock </li>
<li>RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock </li>
<li>RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga2c68fe07259568cba46c14fc4259933d">&#9670;&#160;</a></span>__HAL_RCC_GET_UART5_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_UART5_SOURCE&#160;&#160;&#160;<a class="el" href="#ga2de2c847f3e490a5b6ac8b1d13b66883">__HAL_RCC_GET_USART234578_SOURCE</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to get the UART5 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock </li>
<li>RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock </li>
<li>RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock </li>
<li>RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock </li>
<li>RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock </li>
<li>RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga680abf193deaeff90542affda7d160d4">&#9670;&#160;</a></span>__HAL_RCC_GET_UART7_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_UART7_SOURCE&#160;&#160;&#160;<a class="el" href="#ga2de2c847f3e490a5b6ac8b1d13b66883">__HAL_RCC_GET_USART234578_SOURCE</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to get the UART7 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock </li>
<li>RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock </li>
<li>RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock </li>
<li>RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock </li>
<li>RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock </li>
<li>RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga56b15263e2d6dcc75b362d96bf2f7397">&#9670;&#160;</a></span>__HAL_RCC_GET_UART8_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_UART8_SOURCE&#160;&#160;&#160;<a class="el" href="#ga2de2c847f3e490a5b6ac8b1d13b66883">__HAL_RCC_GET_USART234578_SOURCE</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to get the UART8 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock </li>
<li>RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock </li>
<li>RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock </li>
<li>RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock </li>
<li>RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock </li>
<li>RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga4f9d49aa3d088259c585f7509736818c">&#9670;&#160;</a></span>__HAL_RCC_GET_USART16910_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_USART16910_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;D2CCIP2R, RCC_D2CCIP2R_USART16910SEL)))</div>
</div><!-- fragment -->
<p>macro to get the USART1/6/9* /10* clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock </li>
<li>RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock </li>
<li>RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock </li>
<li>RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock </li>
<li>RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock </li>
<li>RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock</li>
</ul>
(*) : Available on some STM32H7 lines only. </td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga241bae96ad4a1ba687b3bf692e04f444">&#9670;&#160;</a></span>__HAL_RCC_GET_USART1_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_USART1_SOURCE&#160;&#160;&#160;__HAL_RCC_GET_USART16_SOURCE</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to get the USART1 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock </li>
<li>RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock </li>
<li>RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock </li>
<li>RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock </li>
<li>RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock </li>
<li>RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga2de2c847f3e490a5b6ac8b1d13b66883">&#9670;&#160;</a></span>__HAL_RCC_GET_USART234578_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_USART234578_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))</div>
</div><!-- fragment -->
<p>macro to get the USART2/3/4/5/7/8 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock </li>
<li>RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock </li>
<li>RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock </li>
<li>RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock </li>
<li>RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock </li>
<li>RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga59a86a292df891a219d5d4a8e26a45e9">&#9670;&#160;</a></span>__HAL_RCC_GET_USART2_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_USART2_SOURCE&#160;&#160;&#160;<a class="el" href="#ga2de2c847f3e490a5b6ac8b1d13b66883">__HAL_RCC_GET_USART234578_SOURCE</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to get the USART2 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock </li>
<li>RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock </li>
<li>RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock </li>
<li>RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock </li>
<li>RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock </li>
<li>RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga04818c61b18e167ea60f290ab52247db">&#9670;&#160;</a></span>__HAL_RCC_GET_USART3_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_USART3_SOURCE&#160;&#160;&#160;<a class="el" href="#ga2de2c847f3e490a5b6ac8b1d13b66883">__HAL_RCC_GET_USART234578_SOURCE</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to get the USART3 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock </li>
<li>RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock </li>
<li>RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock </li>
<li>RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock </li>
<li>RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock </li>
<li>RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga134c539c1f80f684ee9722f08e4c89ea">&#9670;&#160;</a></span>__HAL_RCC_GET_USART6_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_USART6_SOURCE&#160;&#160;&#160;__HAL_RCC_GET_USART16_SOURCE</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to get the USART6 clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock </li>
<li>RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock </li>
<li>RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock </li>
<li>RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock </li>
<li>RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock </li>
<li>RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga2b796e523b7f4c4cd7b5f06b7f995315">&#9670;&#160;</a></span>__HAL_RCC_GET_USB_SOURCE</h2>

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          <td class="memname">#define __HAL_RCC_GET_USB_SOURCE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((uint32_t)(READ_BIT(RCC-&gt;CDCCIP2R, RCC_CDCCIP2R_USBSEL)))</div>
</div><!-- fragment -->
<p>Macro to get the USB clock source. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">The</td><td>clock source can be one of the following values: <ul>
<li>RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock </li>
<li>RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock </li>
<li>RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gafd775b802b35eddc3763819b696c8dc6">&#9670;&#160;</a></span>__HAL_RCC_I2C1235_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_I2C1235_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__I2C1235CLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__))</div>
</div><!-- fragment -->
<p>macro to configure the I2C1/2/3/5* clock (I2C123CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__I2C1235CLKSource__</td><td>specifies the I2C1/2/3/5* clock source. This parameter can be one of the following values: <ul>
<li>RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock </li>
<li>RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock </li>
<li>RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock </li>
<li>RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock</li>
</ul>
(**): Available on stm32h72xxx and stm32h73xxx family lines. </td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga7cd89ab045ec9b7d5bda7da3e1587828">&#9670;&#160;</a></span>__HAL_RCC_I2C1_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_I2C1_CONFIG&#160;&#160;&#160;__HAL_RCC_I2C123_CONFIG</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to configure the I2C1 clock (I2C1CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__I2C1CLKSource__</td><td>specifies the I2C1 clock source. This parameter can be one of the following values: <ul>
<li>RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock </li>
<li>RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock </li>
<li>RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock </li>
<li>RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga96d9bad1e46c94af8387ca6dbfeea357">&#9670;&#160;</a></span>__HAL_RCC_I2C2_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_I2C2_CONFIG&#160;&#160;&#160;__HAL_RCC_I2C123_CONFIG</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to configure the I2C2 clock (I2C2CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__I2C2CLKSource__</td><td>specifies the I2C2 clock source. This parameter can be one of the following values: <ul>
<li>RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock </li>
<li>RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock </li>
<li>RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock </li>
<li>RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga335a0313bb3a188435b39a11cf7c3eee">&#9670;&#160;</a></span>__HAL_RCC_I2C3_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_I2C3_CONFIG&#160;&#160;&#160;__HAL_RCC_I2C123_CONFIG</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to configure the I2C3 clock (I2C3CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__I2C3CLKSource__</td><td>specifies the I2C3 clock source. This parameter can be one of the following values: <ul>
<li>RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock </li>
<li>RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock </li>
<li>RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock </li>
<li>RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gac63fbd88afa59e3453a7d5d7c32fb1dc">&#9670;&#160;</a></span>__HAL_RCC_I2C4_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_I2C4_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__I2C4CLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))</div>
</div><!-- fragment -->
<p>macro to configure the I2C4 clock (I2C4CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__I2C4CLKSource__</td><td>specifies the I2C4 clock source. This parameter can be one of the following values: <ul>
<li>RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock </li>
<li>RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock </li>
<li>RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock </li>
<li>RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga3ef78c8916149398bba06596863734ab">&#9670;&#160;</a></span>__HAL_RCC_LPTIM1_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_LPTIM1_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__LPTIM1CLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))</div>
</div><!-- fragment -->
<p>macro to configure the LPTIM1 clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__LPTIM1CLKSource__</td><td>specifies the LPTIM1 clock source. This parameter can be one of the following values: <ul>
<li>RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock </li>
<li>RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock </li>
<li>RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock </li>
<li>RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock </li>
<li>RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock </li>
<li>RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gabe82d482e8127576b6ce1f331fcc7e1a">&#9670;&#160;</a></span>__HAL_RCC_LPTIM2_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_LPTIM2_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__LPTIM2CLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))</div>
</div><!-- fragment -->
<p>macro to configure the LPTIM2 clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__LPTIM2CLKSource__</td><td>specifies the LPTIM2 clock source. This parameter can be one of the following values: <ul>
<li>RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock </li>
<li>RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock </li>
<li>RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock </li>
<li>RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock </li>
<li>RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock </li>
<li>RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gac11efaec3a89a1b6d9696eb6e9e8048e">&#9670;&#160;</a></span>__HAL_RCC_LPTIM345_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_LPTIM345_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__LPTIM345CLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__))</div>
</div><!-- fragment -->
<p>macro to configure the LPTIM3/4/5 clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__LPTIM345CLKSource__</td><td>specifies the LPTIM3/4/5 clock source. <ul>
<li>RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock </li>
<li>RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock </li>
<li>RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock </li>
<li>RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock </li>
<li>RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock </li>
<li>RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga36174050acd330e879a5d12bdbfb19c4">&#9670;&#160;</a></span>__HAL_RCC_LPTIM3_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_LPTIM3_CONFIG&#160;&#160;&#160;<a class="el" href="#gac11efaec3a89a1b6d9696eb6e9e8048e">__HAL_RCC_LPTIM345_CONFIG</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>macro to configure the LPTIM3 clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__LPTIM3CLKSource__</td><td>specifies the LPTIM3 clock source. <ul>
<li>RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock </li>
<li>RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock </li>
<li>RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock </li>
<li>RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock </li>
<li>RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock </li>
<li>RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga2859926bab56d03f5d4bfbf0941a0a3f">&#9670;&#160;</a></span>__HAL_RCC_LPUART1_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_LPUART1_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__LPUART1CLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))</div>
</div><!-- fragment -->
<p>macro to configure the LPUART1 clock (LPUART1CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__LPUART1CLKSource__</td><td>specifies the LPUART1 clock source. This parameter can be one of the following values: <ul>
<li>RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock </li>
<li>RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock </li>
<li>RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock </li>
<li>RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock </li>
<li>RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock </li>
<li>RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga6171e2da4b75a993142330025862864f">&#9670;&#160;</a></span>__HAL_RCC_LSECSS_EXTI_CLEAR_FLAG</h2>

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          <td class="memname">#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">WRITE_REG(EXTI-&gt;PR1, <a class="code hl_define" href="group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s.html#ga9b28da23df63fe2a235536edd669d8e9">RCC_EXTI_LINE_LSECSS</a>)</div>
<div class="ttc" id="agroup___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s_html_ga9b28da23df63fe2a235536edd669d8e9"><div class="ttname"><a href="group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s.html#ga9b28da23df63fe2a235536edd669d8e9">RCC_EXTI_LINE_LSECSS</a></div><div class="ttdeci">#define RCC_EXTI_LINE_LSECSS</div><div class="ttdef"><b>Definition</b> stm32h7xx_hal_rcc_ex.h:1633</div></div>
</div><!-- fragment -->
<p>Clear the RCC LSE CSS EXTI flag. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="ga20711e52b237c9c598c87d5329a9700f" name="ga20711e52b237c9c598c87d5329a9700f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga20711e52b237c9c598c87d5329a9700f">&#9670;&#160;</a></span>__HAL_RCC_LSECSS_EXTI_DISABLE_EVENT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">CLEAR_BIT(EXTI-&gt;EMR1, <a class="code hl_define" href="group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s.html#ga9b28da23df63fe2a235536edd669d8e9">RCC_EXTI_LINE_LSECSS</a>)</div>
</div><!-- fragment -->
<p>Disable the RCC LSE CSS Event Line. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="ga5b8a28d3896b67495b996d001084885e" name="ga5b8a28d3896b67495b996d001084885e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5b8a28d3896b67495b996d001084885e">&#9670;&#160;</a></span>__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">CLEAR_BIT(EXTI-&gt;FTSR1, <a class="code hl_define" href="group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s.html#ga9b28da23df63fe2a235536edd669d8e9">RCC_EXTI_LINE_LSECSS</a>)</div>
</div><!-- fragment -->
<p>Disable the RCC LSE CSS Extended Interrupt Falling Trigger. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="gaa5c2a31f367b8085be517e315b8c0196" name="gaa5c2a31f367b8085be517e315b8c0196"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa5c2a31f367b8085be517e315b8c0196">&#9670;&#160;</a></span>__HAL_RCC_LSECSS_EXTI_DISABLE_IT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">CLEAR_BIT(EXTI-&gt;IMR1, <a class="code hl_define" href="group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s.html#ga9b28da23df63fe2a235536edd669d8e9">RCC_EXTI_LINE_LSECSS</a>)</div>
</div><!-- fragment -->
<p>Disable the RCC LSE CSS Extended Interrupt Line. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="ga2746b06cbf0f080a600f3f895c95f3fb" name="ga2746b06cbf0f080a600f3f895c95f3fb"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga2746b06cbf0f080a600f3f895c95f3fb">&#9670;&#160;</a></span>__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">CLEAR_BIT(EXTI-&gt;RTSR1, <a class="code hl_define" href="group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s.html#ga9b28da23df63fe2a235536edd669d8e9">RCC_EXTI_LINE_LSECSS</a>)</div>
</div><!-- fragment -->
<p>Disable the RCC LSE CSS Extended Interrupt Rising Trigger. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="gacea34070069d535080039e3067aba82d" name="gacea34070069d535080039e3067aba82d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gacea34070069d535080039e3067aba82d">&#9670;&#160;</a></span>__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">  <span class="keywordflow">do</span> {                                                       \</div>
<div class="line">    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \</div>
<div class="line">    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \</div>
<div class="line">  } <span class="keywordflow">while</span>(0)</div>
</div><!-- fragment -->
<p>Disable the RCC LSE CSS Extended Interrupt Rising &amp; Falling Trigger. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="gad5f8173d2752512c30375c9ca7890fbc" name="gad5f8173d2752512c30375c9ca7890fbc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad5f8173d2752512c30375c9ca7890fbc">&#9670;&#160;</a></span>__HAL_RCC_LSECSS_EXTI_ENABLE_EVENT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">SET_BIT(EXTI-&gt;EMR1, <a class="code hl_define" href="group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s.html#ga9b28da23df63fe2a235536edd669d8e9">RCC_EXTI_LINE_LSECSS</a>)</div>
</div><!-- fragment -->
<p>Enable the RCC LSE CSS Event Line. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="ga45a0bf105427b24b377125346b2e597d" name="ga45a0bf105427b24b377125346b2e597d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga45a0bf105427b24b377125346b2e597d">&#9670;&#160;</a></span>__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">SET_BIT(EXTI-&gt;FTSR1, <a class="code hl_define" href="group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s.html#ga9b28da23df63fe2a235536edd669d8e9">RCC_EXTI_LINE_LSECSS</a>)</div>
</div><!-- fragment -->
<p>Enable the RCC LSE CSS Extended Interrupt Falling Trigger. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="gafca78bb6fbfed8a31ef7ee030d424b50" name="gafca78bb6fbfed8a31ef7ee030d424b50"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gafca78bb6fbfed8a31ef7ee030d424b50">&#9670;&#160;</a></span>__HAL_RCC_LSECSS_EXTI_ENABLE_IT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">SET_BIT(EXTI-&gt;IMR1, <a class="code hl_define" href="group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s.html#ga9b28da23df63fe2a235536edd669d8e9">RCC_EXTI_LINE_LSECSS</a>)</div>
</div><!-- fragment -->
<p>Enable the RCC LSE CSS Extended Interrupt Line. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="ga14487ed9c109cb494cae4a9762b7c294" name="ga14487ed9c109cb494cae4a9762b7c294"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga14487ed9c109cb494cae4a9762b7c294">&#9670;&#160;</a></span>__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">SET_BIT(EXTI-&gt;RTSR1, <a class="code hl_define" href="group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s.html#ga9b28da23df63fe2a235536edd669d8e9">RCC_EXTI_LINE_LSECSS</a>)</div>
</div><!-- fragment -->
<p>Enable the RCC LSE CSS Extended Interrupt Rising Trigger. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="ga075e9194bfc08b5da32af130a74e7cb4" name="ga075e9194bfc08b5da32af130a74e7cb4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga075e9194bfc08b5da32af130a74e7cb4">&#9670;&#160;</a></span>__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">  <span class="keywordflow">do</span> {                                                      \</div>
<div class="line">    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \</div>
<div class="line">    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \</div>
<div class="line">  } <span class="keywordflow">while</span>(0)</div>
</div><!-- fragment -->
<p>Enable the RCC LSE CSS Extended Interrupt Rising &amp; Falling Trigger. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="gac5a7ed26daae142eb6cce551728ee88c" name="gac5a7ed26daae142eb6cce551728ee88c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac5a7ed26daae142eb6cce551728ee88c">&#9670;&#160;</a></span>__HAL_RCC_LSECSS_EXTI_GENERATE_SWIT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">SET_BIT(EXTI-&gt;SWIER1, <a class="code hl_define" href="group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s.html#ga9b28da23df63fe2a235536edd669d8e9">RCC_EXTI_LINE_LSECSS</a>)</div>
</div><!-- fragment -->
<p>Generate a Software interrupt on the RCC LSE CSS EXTI line. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="ga65fa248e1dd8c7258a50ba03c4e2ff85" name="ga65fa248e1dd8c7258a50ba03c4e2ff85"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga65fa248e1dd8c7258a50ba03c4e2ff85">&#9670;&#160;</a></span>__HAL_RCC_LSECSS_EXTI_GET_FLAG</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_LSECSS_EXTI_GET_FLAG</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(READ_BIT(EXTI-&gt;PR1, <a class="code hl_define" href="group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s.html#ga9b28da23df63fe2a235536edd669d8e9">RCC_EXTI_LINE_LSECSS</a>) == <a class="code hl_define" href="group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s.html#ga9b28da23df63fe2a235536edd669d8e9">RCC_EXTI_LINE_LSECSS</a>)</div>
</div><!-- fragment -->
<p>Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. </p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">EXTI</td><td>RCC LSE CSS Line Status. </td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="ga1b17f7d45a505cc6acce76a1a80d9aca" name="ga1b17f7d45a505cc6acce76a1a80d9aca"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1b17f7d45a505cc6acce76a1a80d9aca">&#9670;&#160;</a></span>__HAL_RCC_PLL2_CONFIG</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __HAL_RCC_PLL2_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__PLL2M__</em></span>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__PLL2N__</em></span>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__PLL2P__</em></span>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__PLL2Q__</em></span>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__PLL2R__</em></span>&#160;)</td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  <span class="keywordflow">do</span>{ \</div>
<div class="line">                       MODIFY_REG(RCC-&gt;PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) &lt;&lt;12U));  \</div>
<div class="line">                       WRITE_REG (RCC-&gt;PLL2DIVR , ( (((__PLL2N__) - 1U ) &amp; RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) &lt;&lt; 9U) &amp; RCC_PLL2DIVR_P2) | \</div>
<div class="line">                       ((((__PLL2Q__) -1U) &lt;&lt; 16U) &amp; RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) &lt;&lt; 24U) &amp; RCC_PLL2DIVR_R2))); \</div>
<div class="line">                    } <span class="keywordflow">while</span>(0)</div>
</div><!-- fragment -->
<p>Macro to configures the PLL2 multiplication and division factors. </p>
<dl class="section note"><dt>Note</dt><dd>This function must be used only when PLL2 is disabled.</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__PLL2M__</td><td>specifies the division factor for PLL2 VCO input clock This parameter must be a number between 1 and 63. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__PLL2N__</td><td>specifies the multiplication factor for PLL2 VCO output clock This parameter must be a number between 4 and 512 or between 8 and 420(*). </td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>You have to set the PLL2N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__PLL2P__</td><td>specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.</td></tr>
    <tr><td class="paramname">__PLL2Q__</td><td>specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.</td></tr>
    <tr><td class="paramname">__PLL2R__</td><td>specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible value to <b>PLL2P</b>, <b>PLL2Q</b> or <b>PLL2R</b> parameters. </dd></dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>
<p>(*) : For stm32h7a3xx and stm32h7b3xx family lines. </p>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga1e44121d27a8d6096c170d4a2e7c1981">&#9670;&#160;</a></span>__HAL_RCC_PLL2_DISABLE</h2>

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          <td class="memname">#define __HAL_RCC_PLL2_DISABLE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">CLEAR_BIT(RCC-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga250f64c1041b823f2bd5dbbb4c54a2d5">RCC_CR_PLL2ON</a>)</div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga250f64c1041b823f2bd5dbbb4c54a2d5"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga250f64c1041b823f2bd5dbbb4c54a2d5">RCC_CR_PLL2ON</a></div><div class="ttdeci">#define RCC_CR_PLL2ON</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:14514</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#gacc1a8ad328f57e3dcade01e5355e0add">&#9670;&#160;</a></span>__HAL_RCC_PLL2_ENABLE</h2>

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          <td class="memname">#define __HAL_RCC_PLL2_ENABLE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">SET_BIT(RCC-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga250f64c1041b823f2bd5dbbb4c54a2d5">RCC_CR_PLL2ON</a>)</div>
</div><!-- fragment -->
<p>Macros to enable or disable PLL2. </p>
<dl class="section note"><dt>Note</dt><dd>After enabling PLL2, the application software should wait on PLL2RDY flag to be set indicating that PLL2 clock is stable and can be used as kernel clock source. </dd>
<dd>
PLL2 is disabled by hardware when entering STOP and STANDBY modes. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga88d12a5c64e4a820268b9f7f50d74179">&#9670;&#160;</a></span>__HAL_RCC_PLL2_VCIRANGE</h2>

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          <td class="memname">#define __HAL_RCC_PLL2_VCIRANGE</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_PLL2VCIRange__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))</div>
</div><!-- fragment -->
<p>Macro to select the PLL2 reference frequency range. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_PLL2VCIRange__</td><td>specifies the PLL2 input frequency range This parameter can be one of the following values: <ul>
<li>RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz </li>
<li>RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz </li>
<li>RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz </li>
<li>RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5b448c0dab856525467ba9146db00432">&#9670;&#160;</a></span>__HAL_RCC_PLL2_VCORANGE</h2>

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          <td class="memname">#define __HAL_RCC_PLL2_VCORANGE</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_PLL2VCORange__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))</div>
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<p>Macro to select the PLL2 reference frequency range. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_PLL2VCORange__</td><td>Specifies the PLL2 input frequency range This parameter can be one of the following values: <ul>
<li>RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) </li>
<li>RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz</li>
</ul>
(*) : For stm32h7a3xx and stm32h7b3xx family lines.</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga20869ea15ad0f090d4e3fcc217242474">&#9670;&#160;</a></span>__HAL_RCC_PLL2CLKOUT_DISABLE</h2>

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          <td class="memname">#define __HAL_RCC_PLL2CLKOUT_DISABLE</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_PLL2ClockOut__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">CLEAR_BIT(RCC-&gt;PLLCFGR, (__RCC_PLL2ClockOut__))</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gadee20de14af30b0f958fda51d852066b">&#9670;&#160;</a></span>__HAL_RCC_PLL2CLKOUT_ENABLE</h2>

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          <td class="memname">#define __HAL_RCC_PLL2CLKOUT_ENABLE</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_PLL2ClockOut__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">SET_BIT(RCC-&gt;PLLCFGR, (__RCC_PLL2ClockOut__))</div>
</div><!-- fragment -->
<p>Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) </p>
<dl class="section note"><dt>Note</dt><dd>Enabling/disabling those Clocks can be done only when the PLL2 is disabled, This is mainly used to save Power. </dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_PLL2ClockOut__</td><td>Specifies the PLL2 clock to be outputted This parameter can be one of the following values: <ul>
<li>RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) </li>
<li>RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) </li>
<li>RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)</li>
</ul>
(*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gac2cb75d60618ffea824634490f9d81eb">&#9670;&#160;</a></span>__HAL_RCC_PLL2FRACN_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_PLL2FRACN_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_PLL2FRACN__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                 MODIFY_REG(RCC-&gt;PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) &lt;&lt; RCC_PLL2FRACR_FRACN2_Pos))</div>
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<p>Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor. </p>
<dl class="section note"><dt>Note</dt><dd>These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_PLL2FRACN__</td><td>Specifies Fractional Part Of The Multiplication factor for PLL2 VCO It should be a value between 0 and 8191 </td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>Warning: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 150 to 420 MHz if PLL2VCOSEL = 1.</dd></dl>
<p>(*) : For stm32h7a3xx and stm32h7b3xx family lines.</p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga320b2becbdbe9830622f1b96526a5d7b">&#9670;&#160;</a></span>__HAL_RCC_PLL2FRACN_DISABLE</h2>

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          <td class="memname">#define __HAL_RCC_PLL2FRACN_DISABLE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line">CLEAR_BIT(RCC-&gt;PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga25e0f4d0ef5f525a3c0c5c0a155d0ac6">&#9670;&#160;</a></span>__HAL_RCC_PLL2FRACN_ENABLE</h2>

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          <td class="memname">#define __HAL_RCC_PLL2FRACN_ENABLE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">SET_BIT(RCC-&gt;PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)</div>
</div><!-- fragment -->
<p>Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO. </p>
<dl class="section note"><dt>Note</dt><dd>Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 </dd></dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gac5020a08025c53436a32d77640786d5d">&#9670;&#160;</a></span>__HAL_RCC_PLL3_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_PLL3_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__PLL3M__</em></span>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__PLL3N__</em></span>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__PLL3P__</em></span>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__PLL3Q__</em></span>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__PLL3R__</em></span>&#160;)</td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  <span class="keywordflow">do</span>{ MODIFY_REG(RCC-&gt;PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) &lt;&lt;20U));  \</div>
<div class="line">                         WRITE_REG (RCC-&gt;PLL3DIVR , ( (((__PLL3N__) - 1U ) &amp; RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) &lt;&lt; 9U) &amp; RCC_PLL3DIVR_P3) | \</div>
<div class="line">                                   ((((__PLL3Q__) -1U) &lt;&lt; 16U) &amp; RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) &lt;&lt; 24U) &amp; RCC_PLL3DIVR_R3))); \</div>
<div class="line">                       } <span class="keywordflow">while</span>(0)</div>
</div><!-- fragment -->
<p>Macro to configures the PLL3 multiplication and division factors. </p>
<dl class="section note"><dt>Note</dt><dd>This function must be used only when PLL3 is disabled.</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__PLL3M__</td><td>specifies the division factor for PLL3 VCO input clock This parameter must be a number between 1 and 63. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__PLL3N__</td><td>specifies the multiplication factor for PLL3 VCO output clock This parameter must be a number between 4 and 512. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>You have to set the PLL3N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__PLL3P__</td><td>specifies the division factor for peripheral kernel clocks This parameter must be a number between 2 and 128 (where odd numbers not allowed)</td></tr>
    <tr><td class="paramname">__PLL3Q__</td><td>specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128</td></tr>
    <tr><td class="paramname">__PLL3R__</td><td>specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible value to <b>PLL3P</b>, <b>PLL3Q</b> or <b>PLL3R</b> parameters. </dd></dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>
<p>(*) : For stm32h7a3xx and stm32h7b3xx family lines. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga9eccd5f7fbfd12da15ba7d76d9a21d18">&#9670;&#160;</a></span>__HAL_RCC_PLL3_DISABLE</h2>

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          <td class="memname">#define __HAL_RCC_PLL3_DISABLE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">CLEAR_BIT(RCC-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga7e7f10468741ab47dc34808af0e49b2b">RCC_CR_PLL3ON</a>)</div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga7e7f10468741ab47dc34808af0e49b2b"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga7e7f10468741ab47dc34808af0e49b2b">RCC_CR_PLL3ON</a></div><div class="ttdeci">#define RCC_CR_PLL3ON</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:14520</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#gac7c3a26323f470a939b021ad76f29518">&#9670;&#160;</a></span>__HAL_RCC_PLL3_ENABLE</h2>

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          <td class="memname">#define __HAL_RCC_PLL3_ENABLE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">SET_BIT(RCC-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga7e7f10468741ab47dc34808af0e49b2b">RCC_CR_PLL3ON</a>)</div>
</div><!-- fragment -->
<p>Macros to enable or disable the main PLL3. </p>
<dl class="section note"><dt>Note</dt><dd>After enabling PLL3, the application software should wait on PLL3RDY flag to be set indicating that PLL3 clock is stable and can be used as kernel clock source. </dd>
<dd>
PLL3 is disabled by hardware when entering STOP and STANDBY modes. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5825c7707fdbf1432a215fbf3ef4b766">&#9670;&#160;</a></span>__HAL_RCC_PLL3_VCIRANGE</h2>

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          <td class="memname">#define __HAL_RCC_PLL3_VCIRANGE</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_PLL3VCIRange__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))</div>
</div><!-- fragment -->
<p>Macro to select the PLL3 reference frequency range. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_PLL3VCIRange__</td><td>specifies the PLL1 input frequency range This parameter can be one of the following values: <ul>
<li>RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz </li>
<li>RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz </li>
<li>RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz </li>
<li>RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga7c53c8f29406ecd9c45434db4b2af32d">&#9670;&#160;</a></span>__HAL_RCC_PLL3_VCORANGE</h2>

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          <td class="memname">#define __HAL_RCC_PLL3_VCORANGE</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_PLL3VCORange__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))</div>
</div><!-- fragment -->
<p>Macro to select the PLL3 reference frequency range. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_PLL3VCORange__</td><td>specifies the PLL1 input frequency range This parameter can be one of the following values: <ul>
<li>RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) </li>
<li>RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz</li>
</ul>
(*) : For stm32h7a3xx and stm32h7b3xx family lines.</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga36d6e5c5786cab7644e5149d00f704c3">&#9670;&#160;</a></span>__HAL_RCC_PLL3CLKOUT_DISABLE</h2>

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          <td class="memname">#define __HAL_RCC_PLL3CLKOUT_DISABLE</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_PLL3ClockOut__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">CLEAR_BIT(RCC-&gt;PLLCFGR, (__RCC_PLL3ClockOut__))</div>
</div><!-- fragment -->
</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga44dba3c4e64245e760eb3e780096b4da">&#9670;&#160;</a></span>__HAL_RCC_PLL3CLKOUT_ENABLE</h2>

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          <td class="memname">#define __HAL_RCC_PLL3CLKOUT_ENABLE</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_PLL3ClockOut__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">SET_BIT(RCC-&gt;PLLCFGR, (__RCC_PLL3ClockOut__))</div>
</div><!-- fragment -->
<p>Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) </p>
<dl class="section note"><dt>Note</dt><dd>Enabling/disabling those Clocks can be done only when the PLL3 is disabled, This is mainly used to save Power. </dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_PLL3ClockOut__</td><td>specifies the PLL3 clock to be outputted This parameter can be one of the following values: <ul>
<li>RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) </li>
<li>RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) </li>
<li>RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)</li>
</ul>
(*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga3c6bb3051b93d8f3051ace7b1611c5c1">&#9670;&#160;</a></span>__HAL_RCC_PLL3FRACN_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_PLL3FRACN_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_PLL3FRACN__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">MODIFY_REG(RCC-&gt;PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) &lt;&lt; RCC_PLL3FRACR_FRACN3_Pos)</div>
</div><!-- fragment -->
<p>Macro to configures PLL3 clock Fractional Part of The Multiplication Factor. </p>
<dl class="section note"><dt>Note</dt><dd>These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_PLL3FRACN__</td><td>specifies Fractional Part Of The Multiplication Factor for PLL3 VCO It should be a value between 0 and 8191 </td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>Warning: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 150 to 420 MHz if PLL3VCOSEL = 1.</dd></dl>
<p>(*) : For stm32h7a3xx and stm32h7b3xx family lines.</p>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga4a2fb65aefcf9fd35d55a5de8000173e">&#9670;&#160;</a></span>__HAL_RCC_PLL3FRACN_DISABLE</h2>

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          <td class="memname">#define __HAL_RCC_PLL3FRACN_DISABLE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line">CLEAR_BIT(RCC-&gt;PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)</div>
</div><!-- fragment -->
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga35af940f02bf692f69ca9cf2dd598f24">&#9670;&#160;</a></span>__HAL_RCC_PLL3FRACN_ENABLE</h2>

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          <td class="memname">#define __HAL_RCC_PLL3FRACN_ENABLE</td>
          <td>(</td>
          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">SET_BIT(RCC-&gt;PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)</div>
</div><!-- fragment -->
<p>Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO. </p>
<dl class="section note"><dt>Note</dt><dd>Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 </dd></dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gae34a5e47c3e3a519bfca1f4313a88f9f">&#9670;&#160;</a></span>__HAL_RCC_RNG_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_RNG_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RNGCLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))</div>
</div><!-- fragment -->
<p>macro to configure the RNG clock (RNGCLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RNGCLKSource__</td><td>specifies the RNG clock source. This parameter can be one of the following values: <ul>
<li>RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock </li>
<li>RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock </li>
<li>RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock </li>
<li>RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga0c98df7eb7d710df2bf05427a4a10bc7">&#9670;&#160;</a></span>__HAL_RCC_SAI1_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_SAI1_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_SAI1CLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))</div>
</div><!-- fragment -->
<p>Macro to Configure the SAI1 clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_SAI1CLKSource__</td><td>defines the SAI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: <ul>
<li>RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL </li>
<li>RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 </li>
<li>RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 </li>
<li>RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC </li>
<li>RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga7754edd5cc00e691c5007f22d3a93d38">&#9670;&#160;</a></span>__HAL_RCC_SDMMC_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_SDMMC_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__SDMMCCLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))</div>
</div><!-- fragment -->
<p>Macro to configure the SDMMC clock. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__SDMMCCLKSource__</td><td>specifies clock source for SDMMC This parameter can be one of the following values: <ul>
<li>RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock </li>
<li>RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga6cf17efbf8f472437732901308320283">&#9670;&#160;</a></span>__HAL_RCC_SPDIFRX_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_SPDIFRX_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_SPDIFCLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))</div>
</div><!-- fragment -->
<p>Macro to Configure the SPDIFRX clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_SPDIFCLKSource__</td><td>defines the SPDIFRX clock source. This clock is derived from system PLL, PLL2, PLL3, or internal OSC clock This parameter can be one of the following values: <ul>
<li>RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL </li>
<li>RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2 </li>
<li>RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3 </li>
<li>RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga8da215b69bc3712d5bb359c66198d374">&#9670;&#160;</a></span>__HAL_RCC_SPI123_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_SPI123_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_SPI123CLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))</div>
</div><!-- fragment -->
<p>Macro to Configure the SPI1/2/3 clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_SPI123CLKSource__</td><td>defines the SPI1/2/3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: <ul>
<li>RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL </li>
<li>RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 </li>
<li>RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 </li>
<li>RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP </li>
<li>RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga9b531a40f565975ef8901b48afddf1cc">&#9670;&#160;</a></span>__HAL_RCC_SPI1_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_SPI1_CONFIG&#160;&#160;&#160;<a class="el" href="#ga8da215b69bc3712d5bb359c66198d374">__HAL_RCC_SPI123_CONFIG</a></td>
        </tr>
      </table>
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<p>Macro to Configure the SPI1 clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_SPI1CLKSource__</td><td>defines the SPI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: <ul>
<li>RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL </li>
<li>RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 </li>
<li>RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 </li>
<li>RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP </li>
<li>RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga03aafcdc3a862d9f10a5d1fcce4b549e">&#9670;&#160;</a></span>__HAL_RCC_SPI2_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_SPI2_CONFIG&#160;&#160;&#160;<a class="el" href="#ga8da215b69bc3712d5bb359c66198d374">__HAL_RCC_SPI123_CONFIG</a></td>
        </tr>
      </table>
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<p>Macro to Configure the SPI2 clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_SPI2CLKSource__</td><td>defines the SPI2 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: <ul>
<li>RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL </li>
<li>RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 </li>
<li>RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 </li>
<li>RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP </li>
<li>RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga72e45b0673f5829c390032f8bbb24f17">&#9670;&#160;</a></span>__HAL_RCC_SPI3_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_SPI3_CONFIG&#160;&#160;&#160;<a class="el" href="#ga8da215b69bc3712d5bb359c66198d374">__HAL_RCC_SPI123_CONFIG</a></td>
        </tr>
      </table>
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<p>Macro to Configure the SPI3 clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_SPI3CLKSource__</td><td>defines the SPI3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: <ul>
<li>RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL </li>
<li>RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 </li>
<li>RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 </li>
<li>RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP </li>
<li>RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gaecfe51f0d81f0130e1a5a06408320b72">&#9670;&#160;</a></span>__HAL_RCC_SPI45_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_SPI45_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_SPI45CLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))</div>
</div><!-- fragment -->
<p>Macro to Configure the SPI4/5 clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_SPI45CLKSource__</td><td>defines the SPI4/5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values: <ul>
<li>RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2 </li>
<li>RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 </li>
<li>RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 </li>
<li>RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI </li>
<li>RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI </li>
<li>RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga04806afde06b2bc3b4e409b81fce5c41">&#9670;&#160;</a></span>__HAL_RCC_SPI4_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_SPI4_CONFIG&#160;&#160;&#160;<a class="el" href="#gaecfe51f0d81f0130e1a5a06408320b72">__HAL_RCC_SPI45_CONFIG</a></td>
        </tr>
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<p>Macro to Configure the SPI4 clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_SPI4CLKSource__</td><td>defines the SPI4 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values: <ul>
<li>RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2 </li>
<li>RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 </li>
<li>RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 </li>
<li>RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI </li>
<li>RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI </li>
<li>RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga14c138363b18bdee29cbb3ec82594b92">&#9670;&#160;</a></span>__HAL_RCC_SPI5_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_SPI5_CONFIG&#160;&#160;&#160;<a class="el" href="#gaecfe51f0d81f0130e1a5a06408320b72">__HAL_RCC_SPI45_CONFIG</a></td>
        </tr>
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<p>Macro to Configure the SPI5 clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_SPI5CLKSource__</td><td>defines the SPI5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values: <ul>
<li>RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2 </li>
<li>RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 </li>
<li>RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 </li>
<li>RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI </li>
<li>RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI </li>
<li>RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>

</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga1170019b0ed2e1301d2284c2af149f33">&#9670;&#160;</a></span>__HAL_RCC_SPI6_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_SPI6_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__RCC_SPI6CLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))</div>
</div><!-- fragment -->
<p>Macro to Configure the SPI6 clock source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__RCC_SPI6CLKSource__</td><td>defines the SPI6 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values: <ul>
<li>RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 </li>
<li>RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 </li>
<li>RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 </li>
<li>RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI </li>
<li>RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI </li>
<li>RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE </li>
<li>RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN (*)</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>
<p>(*) : Available on stm32h7a3xx and stm32h7b3xx family lines. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gac23e7b662783a7131e3e892ff0c21f06">&#9670;&#160;</a></span>__HAL_RCC_SWPMI1_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_SWPMI1_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__SWPMI1CLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))</div>
</div><!-- fragment -->
<p>Macro to configure the SWPMI1 clock. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__SWPMI1CLKSource__</td><td>specifies the SWPMI1 clock source. This parameter can be one of the following values: <ul>
<li>RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock </li>
<li>RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga292ca7c84f192778314125ed6d7c8333">&#9670;&#160;</a></span>__HAL_RCC_TIMCLKPRESCALER</h2>

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          <td class="memname">#define __HAL_RCC_TIMCLKPRESCALER</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__PRESC__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line">                                                 <span class="keywordflow">do</span> {RCC-&gt;CFGR &amp;= ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6d6448d5ee420f8cc87b22b1201f5be2">RCC_CFGR_TIMPRE</a>);\</div>
<div class="line">                                                 RCC-&gt;CFGR |= (__PRESC__);       \</div>
<div class="line">                                                }<span class="keywordflow">while</span>(0)</div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga6d6448d5ee420f8cc87b22b1201f5be2"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga6d6448d5ee420f8cc87b22b1201f5be2">RCC_CFGR_TIMPRE</a></div><div class="ttdeci">#define RCC_CFGR_TIMPRE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:14657</div></div>
</div><!-- fragment -->
<p>Macro to configure the Timers clocks prescalers. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__PRESC__</td><td>specifies the Timers clocks prescalers selection This parameter can be one of the following values: <ul>
<li>RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, else it is equal to 2 x Frcc_pclkx_d2 (default after reset) </li>
<li>RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, else it is equal to 4 x Frcc_pclkx_d2 </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga711b187525b8b788b9f0ca968b1bd648">&#9670;&#160;</a></span>__HAL_RCC_UART4_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_UART4_CONFIG&#160;&#160;&#160;<a class="el" href="#ga67f80d0a54e4800370619e3247e3ae01">__HAL_RCC_USART234578_CONFIG</a></td>
        </tr>
      </table>
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<p>macro to configure the UART4 clock (UART4CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__UART4CLKSource__</td><td>specifies the UART4 clock source. This parameter can be one of the following values: <ul>
<li>RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock </li>
<li>RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock </li>
<li>RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock </li>
<li>RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock </li>
<li>RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock </li>
<li>RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gae6c043e0b4091279d4db065b38b801b1">&#9670;&#160;</a></span>__HAL_RCC_UART5_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_UART5_CONFIG&#160;&#160;&#160;<a class="el" href="#ga67f80d0a54e4800370619e3247e3ae01">__HAL_RCC_USART234578_CONFIG</a></td>
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<p>macro to configure the UART5 clock (UART5CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__UART5CLKSource__</td><td>specifies the UART5 clock source. This parameter can be one of the following values: <ul>
<li>RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock </li>
<li>RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock </li>
<li>RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock </li>
<li>RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock </li>
<li>RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock </li>
<li>RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga60bd7f1550266967e3f87a85afbddb7a">&#9670;&#160;</a></span>__HAL_RCC_UART7_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_UART7_CONFIG&#160;&#160;&#160;<a class="el" href="#ga67f80d0a54e4800370619e3247e3ae01">__HAL_RCC_USART234578_CONFIG</a></td>
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<p>macro to configure the UART5 clock (UART7CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__UART7CLKSource__</td><td>specifies the UART7 clock source. This parameter can be one of the following values: <ul>
<li>RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock </li>
<li>RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock </li>
<li>RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock </li>
<li>RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock </li>
<li>RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock </li>
<li>RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga492a06425e99e15b064d5278cf319722">&#9670;&#160;</a></span>__HAL_RCC_UART8_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_UART8_CONFIG&#160;&#160;&#160;<a class="el" href="#ga67f80d0a54e4800370619e3247e3ae01">__HAL_RCC_USART234578_CONFIG</a></td>
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<p>macro to configure the UART8 clock (UART8CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__UART8CLKSource__</td><td>specifies the UART8 clock source. This parameter can be one of the following values: <ul>
<li>RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock </li>
<li>RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock </li>
<li>RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock </li>
<li>RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock </li>
<li>RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock </li>
<li>RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5d331d1d7b05a87debf939ff00d961d5">&#9670;&#160;</a></span>__HAL_RCC_USART16910_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_USART16910_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__USART16910CLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))</div>
</div><!-- fragment -->
<p>macro to configure the USART1/6/9* /10* clock (USART16CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__USART16910CLKSource__</td><td>specifies the USART1/6/9* /10* clock source. This parameter can be one of the following values: <ul>
<li>RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock </li>
<li>RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock </li>
<li>RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock </li>
<li>RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock </li>
<li>RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock </li>
<li>RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock</li>
</ul>
(*) : Available on some STM32H7 lines only. </td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5c9ff3bd1509df21975b5a86202efd52">&#9670;&#160;</a></span>__HAL_RCC_USART1_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_USART1_CONFIG&#160;&#160;&#160;__HAL_RCC_USART16_CONFIG</td>
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<p>macro to configure the USART1 clock (USART1CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__USART1CLKSource__</td><td>specifies the USART1 clock source. This parameter can be one of the following values: <ul>
<li>RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock </li>
<li>RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock </li>
<li>RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock </li>
<li>RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock </li>
<li>RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock </li>
<li>RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga67f80d0a54e4800370619e3247e3ae01">&#9670;&#160;</a></span>__HAL_RCC_USART234578_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_USART234578_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__USART234578CLKSource__</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))</div>
</div><!-- fragment -->
<p>macro to configure the USART234578 clock (USART234578CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__USART234578CLKSource__</td><td>specifies the USART2/3/4/5/7/8 clock source. This parameter can be one of the following values: <ul>
<li>RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock </li>
<li>RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock </li>
<li>RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock </li>
<li>RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock </li>
<li>RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock </li>
<li>RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gaba22cefcb74b384a2e2fb3d2c51fae54">&#9670;&#160;</a></span>__HAL_RCC_USART2_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_USART2_CONFIG&#160;&#160;&#160;<a class="el" href="#ga67f80d0a54e4800370619e3247e3ae01">__HAL_RCC_USART234578_CONFIG</a></td>
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<p>macro to configure the USART2 clock (USART2CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__USART2CLKSource__</td><td>specifies the USART2 clock source. This parameter can be one of the following values: <ul>
<li>RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock </li>
<li>RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock </li>
<li>RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock </li>
<li>RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock </li>
<li>RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock </li>
<li>RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock </li>
</ul>
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  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gac1a20f806bcd2ec6cc781bab1d99e5b5">&#9670;&#160;</a></span>__HAL_RCC_USART3_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_USART3_CONFIG&#160;&#160;&#160;<a class="el" href="#ga67f80d0a54e4800370619e3247e3ae01">__HAL_RCC_USART234578_CONFIG</a></td>
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<p>macro to configure the USART3 clock (USART3CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__USART3CLKSource__</td><td>specifies the USART3 clock source. This parameter can be one of the following values: <ul>
<li>RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock </li>
<li>RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock </li>
<li>RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock </li>
<li>RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock </li>
<li>RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock </li>
<li>RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock </li>
</ul>
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  </dd>
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<h2 class="memtitle"><span class="permalink"><a href="#ga28d9b1a1ce7ec3639b1d02ca10104704">&#9670;&#160;</a></span>__HAL_RCC_USART6_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_USART6_CONFIG&#160;&#160;&#160;__HAL_RCC_USART16_CONFIG</td>
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<p>macro to configure the USART6 clock (USART6CLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__USART6CLKSource__</td><td>specifies the USART6 clock source. This parameter can be one of the following values: <ul>
<li>RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock </li>
<li>RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock </li>
<li>RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock </li>
<li>RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock </li>
<li>RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock </li>
<li>RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock </li>
</ul>
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  </dd>
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<h2 class="memtitle"><span class="permalink"><a href="#ga1c690ec86648d92efb97d2598a0cb2f1">&#9670;&#160;</a></span>__HAL_RCC_USB_CONFIG</h2>

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          <td class="memname">#define __HAL_RCC_USB_CONFIG</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>__USBCLKSource__</em></span></td><td>)</td>
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<b>Value:</b><div class="fragment"><div class="line">                  MODIFY_REG(RCC-&gt;CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))</div>
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<p>Macro to configure the USB clock (USBCLK). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__USBCLKSource__</td><td>specifies the USB clock source. This parameter can be one of the following values: <ul>
<li>RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock </li>
<li>RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock </li>
<li>RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock </li>
</ul>
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<h2 class="memtitle"><span class="permalink"><a href="#ga39626ad9573958c96dccc66d13b1b6fe">&#9670;&#160;</a></span>RCC_CRS_FLAG_ERROR_MASK</h2>

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          <td class="memname">#define RCC_CRS_FLAG_ERROR_MASK&#160;&#160;&#160;((uint32_t)(<a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga4c4c324494f9c6469e53d225242c73d4">RCC_CRS_FLAG_TRIMOVF</a> | <a class="el" href="group___r_c_c_ex___c_r_s___flags.html#gad49f59e34225920835b69a34f1b4c02b">RCC_CRS_FLAG_SYNCERR</a> | <a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga78549e9f343ad843d6e5d45b4e08433c">RCC_CRS_FLAG_SYNCMISS</a>))</td>
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<p>Clear the CRS specified FLAG. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__FLAG__</td><td>specifies the flag to clear. This parameter can be one of the following values: <ul>
<li><a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga27e1ae14c7854ca42faf5379bea5ac39">RCC_CRS_FLAG_SYNCOK</a> SYNC event OK </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga244c3ca47b8099a79212ab10d8e823c9">RCC_CRS_FLAG_SYNCWARN</a> SYNC warning </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga92be7705ece62c427a262355305527fa">RCC_CRS_FLAG_ERR</a> Error </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga10697d7c12b710c52c26db522c11986b">RCC_CRS_FLAG_ESYNC</a> Expected SYNC </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga4c4c324494f9c6469e53d225242c73d4">RCC_CRS_FLAG_TRIMOVF</a> Trimming overflow or underflow </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___flags.html#gad49f59e34225920835b69a34f1b4c02b">RCC_CRS_FLAG_SYNCERR</a> SYNC error </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___flags.html#ga78549e9f343ad843d6e5d45b4e08433c">RCC_CRS_FLAG_SYNCMISS</a> SYNC missed </li>
</ul>
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<dl class="section note"><dt>Note</dt><dd>RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR </dd></dl>
<dl class="retval"><dt>Return values</dt><dd>
  <table class="retval">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
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<h2 class="memtitle"><span class="permalink"><a href="#ga4c5b57880a8c7e917998d0c6a73351fb">&#9670;&#160;</a></span>RCC_CRS_IT_ERROR_MASK</h2>

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          <td class="memname">#define RCC_CRS_IT_ERROR_MASK&#160;&#160;&#160;((uint32_t)(<a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga031f913312b8af1f38dc7c5adcd716f1">RCC_CRS_IT_TRIMOVF</a> | <a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#gaf464654bbdfda5b86982fc4aa5b5a031">RCC_CRS_IT_SYNCERR</a> | <a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#gac6b25a96e779b2f7ee3223101109ee33">RCC_CRS_IT_SYNCMISS</a>))</td>
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<p>Clear the CRS interrupt pending bits. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">__INTERRUPT__</td><td>specifies the interrupt pending bit to clear. This parameter can be any combination of the following values: <ul>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga772a7eb77eaea0622fb3e3b20275a37f">RCC_CRS_IT_SYNCOK</a> SYNC event OK interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga8b9e2cbfa3fd8d7c18f81685c24a394f">RCC_CRS_IT_SYNCWARN</a> SYNC warning interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga01a198f277ff33e6fd5a9c2a6ad908b9">RCC_CRS_IT_ERR</a> Synchronization or trimming error interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#gadf2de3907d21dfaea6b2444d66adfe13">RCC_CRS_IT_ESYNC</a> Expected SYNC interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#ga031f913312b8af1f38dc7c5adcd716f1">RCC_CRS_IT_TRIMOVF</a> Trimming overflow or underflow interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#gaf464654bbdfda5b86982fc4aa5b5a031">RCC_CRS_IT_SYNCERR</a> SYNC error interrupt </li>
<li><a class="el" href="group___r_c_c_ex___c_r_s___interrupt___sources.html#gac6b25a96e779b2f7ee3223101109ee33">RCC_CRS_IT_SYNCMISS</a> SYNC missed interrupt </li>
</ul>
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